Features of the newly announced Intel 4th Generation Xeon-SP Server CPU
Intel's new CPU (just announced on Jan 10, the 4th Generation Xeon-SP) has a number of new features that have been designed specifically for the Communication Market. This presentation will cover some of the cool features including Advanced Matrix Extensions, Data Streaming Accelerator I/O interface instructions, in memory analytics accelerator Dynamic Load Balancer, Software Guard Extensions and Scalable IO Virtualization to mention only a few.
Lunch is available:
Pre-registered IEEE members $10, IEEE Life members $5.,
Pre-registered IEEE Student Members No cost
Non-members or others not pre-registered $15
Date and Time
Location
Hosts
Registration
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- 3000 Waterview Pkwy
- Richardson, Texas
- United States 75080
- Building: SPN 1
- Starts 26 December 2022 05:00 PM UTC
- Ends 17 January 2023 05:00 AM UTC
- No Admission Charge
Speakers
Larry J Horner
Intel 4th Generation Xeon-SP cool features
Biography:
Larry Horner, Intel Principal Engineer, IEEE Senior Life Member, Region 5 ComSoc Director, Dallas CVT Chair, IEEE NFV/SDN co-chair will be presenting to the members and providing an update on the recently released Intel 4th Generation Xeon-SP processor, formerly known as 'Sapphire Rapids'