SoC Design – Trends, Challenges and First Pass Success
Moore’s law scaling of sub-nanometer design process has enabled the integration of several million transistors with a variety of functionality as a System-On-Chip (SoC). The first generation of SoCs were designed with a single processor, DSP and a large number of reusable IP (Intellectual Property), memory software. The current generation of SoCs have multiple processors, multiple buses, analog components and a large amount of software.
I’ll present the trends and challenges in SoC Design. Will present some thoughts on complexity and provide some ideas for managing the complexity. Will provide a motivation for first pass success and will present some practical approaches for verification. Will also present the Zen and Art of Debugging. We will conclude with the practical ideas with a holistic view for getting it right.
Date and Time
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- 161 Warren Street
- Newark, New Jersey
- United States 07102
- Building: ECEC
- Room Number: 202
- Click here for Map
- Contact Event Host
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Dr. Ajay K. Poddar, Ph.: 201-560-3806, email:akpoddar@ieee.org
Prof. D. Misra, Ph: 973-596-5739, email: dmisra@njit.edu
Prof. Edip Niver, Ph: 973-596-3542, email: edip.niver@njit.edu
- Co-sponsored by NJIT/AP03/MTT17
- Starts 30 March 2015 09:00 PM UTC
- Ends 04 May 2015 09:00 PM UTC
- No Admission Charge
Speakers
Dr. Nagi Naganathan of Avago Technologies
SoC Design – Trends, Challenges and First Pass Success
Moore’s law scaling of sub-nanometer design process has enabled the integration of several million transistors with a variety of functionality as a System-On-Chip (SoC). The first generation of SoCs were designed with a single processor, DSP and a large number of reusable IP (Intellectual Property), memory software. The current generation of SoCs have multiple processors, multiple buses, analog components and a large amount of software.
I’ll present the trends and challenges in SoC Design. Will present some thoughts on complexity and provide some ideas for managing the complexity. Will provide a motivation for first pass success and will present some practical approaches for verification. Will also present the Zen and Art of Debugging. We will conclude with the practical ideas with a holistic view for getting it right.
Biography:
Nagi Naganathan is currently a Principal Engineer with Avago Technologies, Allentown. He has 20+ years of experience with the design of chips for video, networking and storage products. He is currently involved with the design of SoCs for storage products. His areas of interests are SoC Design and Architecture, Low Power and ARM Based designs. He served as an adjunct professor in Rutgers University. He is the Secretary of IEEE Princeton/Central Jersey Section and also the Chair of SSCS Chapter. He received his Phd from Southern Methodist University, Dallas, M.ScE from University of New Brunswick and B.E from University of Madras all in Electrical Engineering.
Email:
Address:Avago Technologies, , Allentown, Pennsylvania, United States
Dr. Nagi Naganathan of Avago Technologies
SoC Design – Trends, Challenges and First Pass Success
Biography:
Email:
Address:Allentown, Pennsylvania, United States
Agenda
5:30 PM: Refreshments and Networking
6:00 PM: Seminar in ECE 202
All Welcome: There is no fee/charge for attending IEEE technical semiar. You don't have to be an IEEE Member to attend. Refreshmen/dinner is free for all attendess. Please invite your friends and colleagues to take advantages of this Invited Talk from Industry.