Acceleration of Encryption Algorithm, Elliptic Curve, Pairing, Post Quantum Cryptoalgorithm (PQC), and Fully Homomorphic Encryption (FHE)

# #Security #digital
Share

Dear Members,

We hope all of you are doing well and healthy.

Your Swiss Solid State Circuit Society chapter is having a Busy week with the lecturer visiting for the Commemorative Lecturers for Transistor 75th Anniversary.

On Wednesday 29th of March we are delighted to Host Prof Makoto Ikeda

The topic of the lecture is : " Acceleration of Encryption Algorithm, Elliptic Curve, Pairing, Post Quantum Cryptoalgorithm (PQC), and Fully Homomorphic Encryption (FHE) "

Please Join at 15:00 PM [CET] at ETH Zurich LFW Building, Room B-3 Universitätstrasse 2

The Agenda is as follow:

14:50 - 15:00 Welcome participants

15:00 - 16:00 Lecture

16:00 - 16:30 Questions / Discussion

The event will not be Broadcasted.

We look forward meeting you and having fruitful discussion.

Kind regards,

Mathieu Coustans

For your IEEE Switzerland Solid State Circuit Society committee


  Date and Time

  Location

  Hosts

  Registration


  • Date: 29 Mar 2023
  • Time: 03:00 PM to 04:00 PM
  • All times are (UTC+02:00) Bern
  • Add_To_Calendar_icon Add Event to Calendar
  • ETH Zurich
  • Universitätstrasse 2
  • Zurich , Switzerland
  • Switzerland
  • Building: LFW Building
  • Room Number: Room B-3
  • Contact Event Host
  • Starts 20 March 2023 09:54 PM
  • Ends 29 March 2023 11:00 AM
  • All times are (UTC+02:00) Bern
  • No Admission Charge

  Speakers

Makoto Ikeda

Topic:

Acceleration of Encryption Algorithm, Elliptic Curve, Pairing, Post Quantum Cryptoalgorithm (PQC), and Fully Homomorphic

This lecture will cover basics of public-key encryption, and example design optimization of elliptic-curve based encryption algorithm, including pairing operations, and its security measures. Then extend design optimization on lattice-based encryption algorithms including post quantum crypto-algorithm, and fully homomorphic encryption algorithm.

Biography:

Makoto Ikeda received the BE, ME, and Ph.D. degrees in electrical engineering from the University of Tokyo, Tokyo, Japan, in 1991, 1993 and 1996, respectively. He joined the University of Tokyo as a research associate, in 1996, and now professor at Systems Design Lab (d.lab), the University of Tokyo. At the same time he has been involving the activities of VDEC(VLSI Design and Education Center, the University of Tokyo), to promote VLSI design educations and researches in Japanese academia. He worked for hardware security, asynchronous circuits design, smart image sensor for 3-D range finding, and time-domain signal processing. He has been serving various positions of various international conferences, including ISSCC ITPC Chair, IMMD sub-committee chair (ISSCC 2015 - ), A-SSCC 2015 TPC Chair, VLSI Circuits Symposium PC Chair. He is a member of IEEE, IEICE Japan, IPSJ and ACM.