IEEE EPS Nordic Chapter Distinguished Lecture: Lateral Communications (Bridges) between Chiplets and Heterogeneous Integration Packaging

#Lateral #Communications #Chiplets #Heterogeneous #Integration
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Distinguished Lecture by Prof. John H Lau at NordPac 2023. The slides can be accessed at IEEE EPS Distinguished Lecture Prof. John Lau 20230613


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  • Date: 13 Jun 2023
  • Time: 04:00 PM to 05:00 PM
  • All times are (UTC+02:00) Stockholm
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  • https://nordic.imapseurope.org/distinguished-lecture-nordpac2023/

  • Co-sponsored by NordPac 2023

  Speakers

Prof. John H Lau Prof. John H Lau of Unimicron Technology Corporation

Topic:

Lateral Communications (Bridges) between Chiplets and Heterogeneous Integration Packaging

Chiplet is a chip design method and heterogeneous integration is a chip packaging method. Chiplet design and heterogeneous integration packaging have been generated lots of tractions lately. For the next few years, we will see more implementations of a higher level of chiplet designs and heterogeneous integration packaging, whether it is for cost, time-to-market, performance, form factor, or power consumption. In this lecture, the following topics will be covered.
  • System-on-Chip (SoC)
  • Why Chiplet Design?
  • Chiplet Design and Heterogeneous Integration Packaging – Chip Partition and Chip Split
    • Chip partition and Heterogeneous Integration
    • Chip split and Heterogeneous Integration
    • Advantages and Disadvantages
  • Lateral Communication between Chiplets (e.g., Bridges)
    • Bridge Embedded in Build-up Package Substrate
    • Bridge Embedded in Fan-Out EMC with RDLs
    • UCIe
    • Hybrid Bonding Bridge
  • Chiplet Design and Heterogeneous Integration Packaging - Multiple System and Heterogeneous Integration
    • Multiple System and Heterogeneous Integration with Package Substrate (2D IC Integration)
    • Multiple System and Heterogeneous Integration with Thin Film layer on the Package Substrate (2.1D IC Integration)
    • Multiple System and Heterogeneous Integration with TSV-less (Organic) Interposer (2.3D IC Integration)
    • Multiple System and Heterogeneous Integration with Passive TSV-Interposer (2.5D IC Integration)
    • Multiple System and Heterogeneous Integration with Active TSV-Interposer (3D IC Integration)
  • Summary
  • Potential R&D Topics in Chiplet Design and Heterogeneous Integration Packaging

Biography:

Prof. John H Lau, with more than 40 years of R&D and manufacturing experience in semiconductor packaging, has published more than 517 peer-reviewed papers (375 are the principal investigator), 52 issued and pending US patents (30 are the principal inventor), and 23 textbooks (all are the first author), e.g., Chiplet Design and Heterogeneous Integration Packaging (525 pages, Springer, 2023). John is an elected IEEE fellow, IMAPS Fellow, and ASME Fellow and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share. 

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