IEEE EDS MALAYSIA Mini Colloquium 2023
IEEE EDS Malaysia Chapter proudly invites all of you to the Mini Colloquium 2023. This event is the hybrid mode with three prominent speaker i.e Prof. Dr. Mayank, Prof. Dr. Nowshad, and Prof. Dr. Francesca. It's going to be a really great event and very informative. There will be a lucky draw for those who join the physical. We look forward to seeing you there!
Date and Time
- Date: 29 Aug 2023
- Time: 03:00 PM to 06:30 PM
- All times are (UTC+08:00) Kuala Lumpur
- Add Event to Calendar
Online meeting link (Microsoft Teams)
Meeting ID: 445 144 708 887
- Holiday Villa Hotel
- Lot 1698, Jl. Teluk Baru,
- Pantai Tengah, 07000 Langkawi, Kedah, Kedah
- Malaysia 07000
- Room Number: Main Hall
- Starts 03 August 2023 04:11 PM
- Ends 28 August 2023 04:11 AM
- All times are (UTC+08:00) Kuala Lumpur
- No Admission Charge
lacopi of University of Technology Sydney
Graphene on cubic silicon carbide: integrated functionalities on silicon
Harnessing graphene’s properties on a silicon platform could deliver a broad range of novel miniaturized and in-situ reconfigurable
functionalities. We will review the learnings from the development of our epitaxial graphene on silicon carbide on silicon technology
and some of its most promising applications. This platform allows to obtain any complex graphene -coated silicon carbide 3D
nanostructures in a site – selective fashion at the wafer -scale and with sufficient adhesion for integration [1, 2]. Key capabilities for
nano-optics and metasurfaces in the MIR are specifically unlocked by the graphene/silicon carbide combination .
We have recently demonstrated that the sheet resistance of epitaxial graphene on 3C-SiC on silicon is comparable to that of epitaxial
graphene on SiC wafers, despite substantially smaller grains. We also indicate that the control of the graphene interfaces, particularly
when integrated, can be a more important factor than achieving large grain sizes . In addition, we show that well- engineered
defects in graphene are preferable to defect -free graphene for most electrochemical applications, including biosensing. Promising
examples of application of this technology in the More- than -Moore domain include integrated energy storage , MIR sensing and
detection , and sensors for electro-encephalography [7, 8] for brain-computer interfaces .
 B.Cunning et al, Nanotechnology 25 (32), 325301, 2014  F.Iacopi et al, Journal of Materials Research 30 (5), 609-616, 2015
 P.Rufangura e al, Journal of Physics: Materials 3 (3), 032005, 2020  A.Pradeepkumar et al, ACS Applied Nano Materials 3 (1), 830-841, 2019
 M.Amjadipour, D.Su and F.Iacopi, Batteries & Supercaps 3 (7), 587-595, 2020  P.Rufangura et al, Nanomaterials 11 (9), 2339, 2021 
S.Faisal et al, Journal of Neural Engineering 18 (6), 066035, 2021  S.Faisal et al, ACS Appl. Nano Mater. 5, 8, 10137–10150, 2022  F.Iacopi
and CT Lin, Progress in Biomedical Eng. 2022, doi.org/10.1088/2516-1091/ac993d.
Prof. Francesca Iacopi (PhD in EE, KULeuven, 2004) has 20 years’ experience in Materials and Devices for Semiconductor Technologies across industry and academia, with over 120 peer-reviewed publications and 9 granted patents. Her research emphasis is the translation of basic scientific advances in nanomaterials and novel device concepts into a wide range semiconductor technologies, covering Cu/Low-k interconnects, novel TFET devices, advanced packaging and heterogeneous integration. Research Scientist at IMEC (Belgium) over 1999-2009, she then took up a one -year Guest Professorship at the University of Tokyo (Japan). In 2010-2011 she directed the Chip-Package Interaction strategy for GLOBALFOUNDRIES (Ca, USA), before becoming full -time Academic in Australia in 2012, where she invented a process to obtain graphene on silicon wafers, with applications in integrated sensing and energy storage. She was recipient of an MRS Gold Graduate Student Award (2003), an Australian Research Council Future Fellowship (2012), and a Global Innovation Award at TechConnect in Washington DC (2014). She is a Fellow of the Institution of Engineers Australia, Senior Member IEEE and she is currently Head of Discipline, Communications and Electronics, of the Faculty of Engineering and IT at the University of Technology Sydney.
Address:University of Technology Sydney, , Sydney, Australia
Nowshad of University of Science and Technology Chittagong
Thin Film Photovoltaic (PV) Technology – From Inception to Successful Commercialization of CdTe
Researchers have been working rigorously to achieve the utmost benefit from solar photovoltaic technology in terms of conversion efficiency at the least production cost, since the inception of the first solar photovoltaic (PV) cell in Bell Labs with efficiency of 6% in 1954. Consequently, mega to giga watt-peak (Wp) large-scale solar (LSS) farms have become reality in many countries to date. The so-called first-generation solar cells are mainly using crystalline or multi-crystalline silicon as base materials that are dominating the major market share over 90%. However, the quest for other options in terms of highly absorbent and low cost materials has brought over many other potential candidates such as amorphous silicon (a-Si), cadmium telluride (CdTe), copper-indium-selenide (CIS) as the second generation thin film solar cell technologies since early 70s. Semiconductor materials and their fabrication technologies in many ways have evolved over the time that also have been supporting various wings of solar PV R&D in both conventional and futuristic ways. Some of the thin film photovoltaics are now in commercialization stage owing to their conversion efficiency achievement over 20%, although Shockley–Queisser limit shows up to 30%. Moreover, new arena has been opened up for the most challenging but prospective device structures such as graded bandgap and tandem/multi-junctions of various materials. Taking binary semiconductor of CdTe as an example as one of the leading thin film solar cell technologies, the presentation will show the chronological development since its inception. Various fabrication processes, such as close-spaced sublimation, sputtering or vapor transport evaporation of the CdTe absorber layer along with its most suitable n-type partner of cadmium sulphide (CdS) and other supporting layers will be elaborated. The prospects as well as limitations will be discussed to achieve the highest conversion efficiency with all options in its structural configuration. The standard and stable structure of CdTe thin film solar cells has entered towards successful commercialization of Giga Wp scale annual production almost a decade ago, however with a number of unresolved issues. Issues that can further improve the efficiency as well as future direction of R&D will be introduced. This will definitely elevate the hope for thin film solar photovoltaic technology amid the imminent energy crisis around the world besides promoting enthusiasm within research community.
Dr. Nowshad Amin (S'1999_M'2007_SM'2019) is the head of Solar Energy Research Unit of the Institute of Sustainable Energy at the Universiti Tenaga Nasional (@ UNITEN, The National Energy University) of Malaysia. After higher-secondary-education from his native country Bangladesh, he received the Japanese Ministry of Education (MONBUSHO) scholarship in 1990 to study Electrical Engineering, where he achieved BSc (1996) from Toyohashi University of Technology, followed by Masters (1998) and PhD (2001) from Tokyo Institute of Technology, Japan. His areas of expertise include Renewable Energy, Solar Photovoltaic Cells’ Fabrication and Application. He worked for Motorola Japan ltd as well as served as the CTO of a University Spin-off company financed by Malaysian Technology Development Corporation (MTDC). Apart from teaching over 16 years, he has been leading numerous government (Malaysia) and international (NSF-USA, Qatar Foundation, Saudi Arabia-NPST) funded projects. He is actively involved in promoting Solar Energy in South and South-East Asian countries.
Address:University of Science and Technology Chittagong, , Chittagong, Bangladesh
A Roadmap for Disruptive Applications and Heterogeneous Integration Using Two-Dimensional Materials: State-of-the-Art an
This talk will attempt to establish a roadmap for 2-Dimensional (2D) material-based Nanoelectronic technologies for beyond Si and other future/disruptive applications with a vision for the semiconductor industry to enable a universal technology platform for heterogeneous integration. The heterogeneous integration would involve integrating orthogonal capabilities such as different forms of computing (classical, neuromorphic and quantum), all forms of sensing, digital and analog memories, energy harvesting, etc. – all in a single chip using a universal technology platform. This talk will also cover the technological and fundamental challenges in pushing the 2D technology to the market, where the world stands today, and what gaps are required to be filled. Talking about the gaps, I will particularly touch base on the Metal (3D) to graphene/TMD (2D) contact engineering challenges, which has been considered as one of the most fundamental challenges towards harnessing the full potential of 2-dimensional materials. And, how the fundamental understanding of the contact's quantum chemistry resulted in unique ways to engineer it, resulting into record transistor performance. Besides, I will talk about some of the fundamental process challenges which can unintentionally perturb the 2D channel’s electrical, optical and mechanical properties. In the end, I will talk about some of the reliability gaps, which are urgently required to be addressed and the fundamental understanding we have developed so far.
Prof. Mayank Shrivastava is a faculty member at the Indian Institute of Science, Bangalore, and co-founder of AGNIT Semiconductors Pvt. Ltd. He is also instrumental in setting up a 300 Crore worth GaN prototyping Fab and leading a national effort on 2D material’s technology hub. He received his Ph.D. degree from the Indian Institute of Technology Bombay (2010). For his Ph.D. work, he received Excellence in Research award and the Industrial Impact award from IIT Bombay in 2010. He is among the first recipients of the Indian section of the American TR35 award (2010) and the first Indian to receive IEEE EDS Early Career Award (2015). He is also an Editor of IEEE Transactions on Electron Devices. Besides, he is an IEEE Electron Device’s Society (EDS) Distinguished Lecturer and an elected member of the IEEE EDS Board of Governors. He is the recipient of the prestigious DST Swarnjayanti Fellowship (2021), Abdul Kalam Technology Innovation National Fellowship from INAE-SERB (2021), and the VASVIK award (2021). He has received several other national awards and honors of high repute, like the National Academy of Sciences, India, (NASI) Young Scientist Platinum Jubilee Award – 2018; Indian National Academy of Science (INSA) Young Scientist Award - 2018; Indian National Academy of Engineering (INAE) Innovator Entrepreneur Award 2018 (Special commendation); Indian National Academy of Engineering (INAE) Young Engineer Award - 2017; INAE Young Associate (since 2017); Indian Academy of Sciences (IASc), Young Associate, 2018 – 2023; Ministry of Electronics & Information Technology (MeitY), Young Faculty Fellowship. Besides, he received best paper awards from several international conferences like Intel Corporation Asia academic forum, VLSI design Conference and EOSESD Symposium. Prof Shrivastava broadly works on applications of emerging materials like Gallium Nitride (GaN), atomically thin two-dimensional materials like Graphene and TMDCs, in electronic and electro-optic devices working closer to its fundamental limits (like the ability to handle extreme powers, ability to work at THz like ultra-high frequencies, or ability to compute information in unconventional ways). Currently, his group is developing few-atom thick devices & circuits, GaN-based ultra-high-power devices with high reliability, and devices/circuits for operation at THz frequencies. Besides, his group also works on developing novel ESD and High Voltage device concepts in advanced CMOS nodes. He held visiting positions in Inﬁneon Technologies, Munich, Germany, from April 2008 to October 2008 and again from May 2010 to July 2010. He worked for Inﬁneon Technologies, East Fishkill, NY, USA; IBM Microelectronics, Burlington, VT, USA; Intel Mobile Communications, Hopewell Junction, NY, USA; Intel Corp, Mobile and Communications Group, Munich, Germany between 2010 and 2013. He joined the Indian Institute of Science as a faculty member in the year 2013. Prof Shrivastava’s work has resulted in over 200 peer-reviewed publications (47 of these papers are in IRPS and IEDM, the two most prestigious conferences of IEEE EDS, and around 100 are in journals such as IEEE T-ED) and 47 patents. Most of these patents are either licensed by semiconductor companies or are in use in their products
Address:Indian Institute of Science Bangalore, , Bangalore, India, 560012
29th August 2023
- MQ program - DL talk ( 3pm – 6pm)
- 3.00pm – 4.00pm (Prof. Francesca - virtual)
- 4.00pm – 5.00pm (Prof Nowshad - virtual)
- 5.00pm – 6.00pm (Prof. Mayank)
- 6.30pm Program end