Driving Automotive ICs into Advanced CMOS
Automotive processors have become a multi-billion dollar market with ever growing demand for advanced silicon. Cars today are increasingly featured with better safety/autonomy, electrification, and connectivity. In this talk, we will cover how automotive electronics is evolving towards domain and zonal topologies to integrate more functionality, and provide a brief overview of NXP's portfolio to enable this evolution. We will discuss the opportunities and challenges that accompany the migration of these very cost-sensitive products to advanced CMOS nodes incorporating the fully depleted finFET. We will also summarize the key process technology elements that have enabled the advanced finFET CMOS nodes, highlighting the resulting device technology characteristics and challenges impacting design.
Date and Time
Location
Hosts
Registration
- Date: 21 Sep 2023
- Time: 02:00 PM to 03:30 PM
- All times are (UTC-07:00) Pacific Time (US & Canada)
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- 2356 Main Mall
- Vancouver, British Columbia
- Canada V6T 1Z4
- Building: MacLeod Building
- Room Number: 3038
- Starts 20 September 2023 06:00 AM
- Ends 21 September 2023 02:00 PM
- All times are (UTC-07:00) Pacific Time (US & Canada)
- No Admission Charge
Speakers
Alvin Loke of NXP Semiconductors
Driving Automotive ICs into Advanced CMOS
Automotive processors have become a multi-billion dollar market with ever growing demand for advanced silicon. Cars today are increasingly featured with better safety/autonomy, electrification, and connectivity. In this talk, we will cover how automotive electronics is evolving towards domain and zonal topologies to integrate more functionality, and provide a brief overview of NXP's portfolio to enable this evolution. We will discuss the opportunities and challenges that accompany the migration of these very cost-sensitive products to advanced CMOS nodes incorporating the fully depleted finFET. We will also summarize the key process technology elements that have enabled the advanced finFET CMOS nodes, highlighting the resulting device technology characteristics and challenges impacting design.
Biography:
Dr. Alvin Loke is a Fellow at NXP Semiconductors in San Diego, having worked on CMOS nodes spanning 250nm to 2nm. He received his B.A.Sc. (Eng. Physics) with highest honors from the University of British Columbia, and M.S. and Ph.D. from Stanford. Upon graduating, he spent several years in CMOS process integration. Since 2001, he has worked on analog/mixed-signal design focusing on a variety of wireline links, design/model/technology interface, and analog design methodologies at Agilent, AMD, Qualcomm, TSMC, and now NXP. He has been an active IEEE Solid-State Circuits Society (SSCS) volunteer since 2003, having served as Distinguished Lecturer, AdCom Member, CICC Committee Member, Webinar Chair, Denver and San Diego Chapter Chair, as well as JSSC, SSCL, and SSC Magazine Guest Editor. He currently serves in the VLSI Symposi
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