Dr. Clifford Lau of Institute for Defense Analyses

Semiconductor microelectronic chips are critical components in defense C4ISR and weapon systems.  Department of Defense (DoD) needs to have an assured supply of advanced microcroelectronic chips, in peacetime and wartime.  Since DoD itself normally does not make the chips, DoD depends on the semiconductor industry to produce the needed chips.  DoD uses a variety of chips, many are commercial-off-the-shelf (COTS) and some are classified and defense-unique chips.  The semiconductor industry, although originally created by DoD, for several decades has gradually moved off-shore, including fabrication, testing, and packaging.  The U.S. market share of global semiconductor manufacturing capacity has fallen from about 38% in 1990 to 12% in 2020.  TSMC in Taiwan is the world’s largest semiconductor chip manufacturer, supplying 92% of worlds sub-nanometer advanced chips.  To bring semiconductor manufacturing back to the U.S.,  Congress passed the CHIPS and Science Act to reshore semiconductor manufacturing to the U.S. The CHIPS Act authorizes more than $200B, and immediately appropriates $53.7B,  in federal funding to promote domestic semiconductor manufacturing production, DoD allocated $2B as a part of the CHIPS Act.  DoD's Microelectronics Commons initiative selected eight regional innovations hubs that include a large number of members in the industrial base.  The objective of these hubs, called “lab to fab”, is to speed up the transition of microelectronics from research to prototyping to production, and is focused on strengthening the defense microelectronics industrial base.

Biography:

Dr. Clifford Lau is a research staff member at the Institute for Defense Analyses (IDA) performing studies and analyses to support the Office of Secretary of Defense and other defense and federal agencies. Prior to joining IDA, he spent a long career as scientific officer and program director in the Office of Naval Research (ONR) managing various basic science research programs in electronics, computers, and signal processing.  He also spent six years as senior scientist at DDR&E managing the MURI, DURIP, and other defense S&T programs.  He received his Ph.D. from UC Santa Barbara in 1978, M.S. from UC Berkeley in 1967, and B.S. from UC Berkeley in 1966, all in electrical engineering and computer science.  He has published 56 papers and edited 7 books on neural networks and fault tolerant computing.  In his 50 years of IEEE membership, he has served in various capacities, including serving as President of the IEEE Neural Networks Council (now the Computational Intelligence Society) in 1999-2000, President of the IEEE Nanotechnology Council in 2004, Vice President in Circuits and Systems Society in 1996-1997. He was a member of IEEE TAB in 1999-2000 and 2004.  He served as associate editors and guest editors for various IEEE Transactions, including TNN, TAC, TCAS, and Proceedings.  He was on the Editorial Board of the Proceedings of the IEEE in 1988-1996.  He was General Chair for several major IEEE conferences, including IEEE-NANO and IJCNN.  He was chair of IEEE-USA R&D Policy Committee in 2004-2006.  In 2007 he was the IEEE-USA Vice President for Technology Policy.  He is a Life Fellow of the IEEE.