IEEE SSCS Guangzhou Chapter Successfully Organized the IC Design Session in the Doctoral Academic Forum
On September 3rd, 2023, at Sun Yat-sen University, Guangzhou, China, the IEEE Solid-State Circuits Society (SSCS) Guangzhou Chapter successfully organized the IC Design Session in the 12th National Electronic Information Doctoral Academic Forum. The session was chaired by Prof. Jianping Guo, the vice chairperson of SSCS Guangzhou chapter.
The first presentation was given by Dr. Ai He, who was graduated from Peking University, Beijing, China. She is an IC designer with Guangdong Greater Bay Area Institute of Integrated Circuit and System (GIICS). The presentation title is "Design of the 50Gbps PAM4 SerDes." The presentation showcased various optimization technologies for SerDes.
The second presentation, "A Scalable Multi-Chiplet Deep Learning Accelerator with Hub-Side 2.5-D Heterogeneous Integration," was given by Zhanhong Tan from Tsinghua University, Beijing, China. The presentation showed a proposed seven-Chiplet accelerator achieving a peak performance of 10/20/40 TOPS for INT16/8/4. New chiplet designs dramatically increase the computational capability of the system to meet the needs of artificial intelligence.
The third presentation, "An 8-MS/s 16-bit Area-Efficient SAR ADC in 180-nm Process," was made by Siji Huang from the Hong Kong University of Science and Technology (HKUST), Hong Kong SAR, China. The proposed ADC has improved SAR speed and better SNDR performance.
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- Room 212, JIE Building
- 132 Outer Ring East Road, University City, Panyu District
- Guangzhou, Guangdong
- China 510006
- Building: JIE Building
- Room Number: 212
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- Co-sponsored by Jianping Guo
Speakers
Ai He of Guangdong Greater Bay Area Institute of Integrated Circuit and System
Design of the 50Gbps PAM4 SerDes
The presentation showcased various optimization technologies for SerDes.
Biography:
Dr. Ai He is an IC design engineer at the Guangdong Greater Bay Area Institute of Integrated Circuit and System. She obtained her Ph.D. in Microelectronics and Solid-state Electronics from Peking University, and received B.Eng. degree in Microelectronics from Sun Yat-sen University. Dr. He's research interests include high-speed SerDes design and ADC design.
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Siji Huang of Hong Kong University of Science and Technology
An 8-MS/s 16-bit Area-Efficient SAR ADC in 180-nm Process
The proposed ADC shown in the presentation has improved SAR speed and better SNDR performance.
Biography:
Siji Huang received the B.E. degree in microelectronics from Sun Yat-sen University, Guangzhou, China, in 2019. He is currently working towards the Ph.D. degree at the Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology. His research interests include high-precision and high-speed SAR ADCs, and mixed-signal integrated circuits design.
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