Yunteng Huang of Silicon Labs

Monolithic Phase Locked Loop (PLL) is an essential part in almost all modern electronics systems such as microprocessors, RF, optics, and communications systems. PLL technologies have seen great advancement particularly in the last decade with the exploitation of digital PLL architecture. Digital PLLs have now been widely adopted in embedded and cellular applications thanks to its architectural advantages in integration, ease of use, small footprint, low cost and system robustness. Despite these advantages, technology challenges in achieving the best phase noise and spurious performance had limited digital PLLs application outside the most demanding applications such as wireless base stations, coherent optics and high speed communications until now. In this talk, latest technology development in high performance digital PLLs will be presented. The 4th generation DSPLL technology from Silicon Labs delivers phase noise and spur performance exceeding the requirements in LTE wireless base stations, and delivers sub-100fs jitter performance that satisfies the most demanding high speed communications applications while maintaining the ultimate frequency and PLL configuration flexibility. The architecture also allows seamless timing synthesis from multiple timing sources such as GPS, TCXO, XO and LC oscillator all at the same time, making it ideal solution for precision synchronization in wireless infrastructure.

Biography:

Yunteng Huang, has served in various technical and management capacities in Silicon Labs for 15 years. He led the design of a number of timing products, as well as broadcast, wireline and wireless products. In his current role as a distinguished engineer and business development director, he focuses on new product vectors for the company’s long term growth. Prior to Silicon Labs, Yunteng worked as a design engineer at Rockwell, Conexant and Newport Communications (Broadcom). He is the inventor or co-inventor of 36 US patents and co-authored a dozen IEEE journal and conference papers. He holds a Ph.D degree in Electrical Engineering from Oregon State University, B.S EE from Shanghai Jiaotong University. He also holds a MBA from the Wharton School of Business. 

Email: