Driving 224G System Design with Next-Gen TDR Solutions

#BER #BERTS #Bit #Error #Rate #Eye #Pattern #Transceiver #Fiber #Optics
Share

Impedance mismatches, skew, and discontinuities at 224Gbps/lane are more pronounced than ever before. Any of these discrepancies can compromise Insertion loss, Signal-to-Noise Ratio (SNR), and contribute to complex troubleshooting, creating much tighter margins for error in System design. Being able to properly account for these constraints will result in a faster time to market for 224Gbps systems.

This MultiLane webinar explores the challenges of host design where tight margins must be considered, and provides an overview of using TDR analysis to accelerate fault detection and troubleshooting in production testing: streamlining complexity with high-throughput solutions.


  Date and Time

  Location

  Hosts

  Registration


  • Add_To_Calendar_icon Add Event to Calendar
If you are not a robot, please complete the ReCAPTCHA to display virtual attendance info.
  • Contact Event Host
  • Co-sponsored by CH01232 - North Jersey Section Chapter,IM09
  • Starts 05 January 2024 07:00 PM UTC
  • Ends 25 January 2024 05:00 PM UTC
  • No Admission Charge

  Speakers

Nour Sakhr

Topic:

Driving 224Gbps System Design with Next-Gen TDR Solutions

Impedance mismatches, skew, and discontinuities at 224Gbps/lane are more pronounced than ever before. Any of these discrepancies can compromise Insertion loss, Signal-to-Noise Ratio (SNR), and contribute to complex troubleshooting, creating much tighter margins for error in System design. Being able to properly account for these constraints will result in a faster time to market for 224Gbps systems.

This MultiLane webinar explores the challenges of host design where tight margins must be considered, and provides an overview of using TDR analysis to accelerate fault detection and troubleshooting in production testing: streamlining complexity with high-throughput solutions.

Biography:

Field Application Engineer, MultiLane




Agenda

Impedance mismatches, skew, and discontinuities at 224Gbps/lane are more pronounced than ever before. Any of these discrepancies can compromise Insertion loss, Signal-to-Noise Ratio (SNR), and contribute to complex troubleshooting, creating much tighter margins for error in System design. Being able to properly account for these constraints will result in a faster time to market for 224Gbps systems.

This MultiLane webinar explores the challenges of host design where tight margins must be considered, and provides an overview of using TDR analysis to accelerate fault detection and troubleshooting in production testing: streamlining complexity with high-throughput solutions.