Driving 224G System Design with Next-Gen TDR Solutions
Impedance mismatches, skew, and discontinuities at 224Gbps/lane are more pronounced than ever before. Any of these discrepancies can compromise Insertion loss, Signal-to-Noise Ratio (SNR), and contribute to complex troubleshooting, creating much tighter margins for error in System design. Being able to properly account for these constraints will result in a faster time to market for 224Gbps systems.
This MultiLane webinar explores the challenges of host design where tight margins must be considered, and provides an overview of using TDR analysis to accelerate fault detection and troubleshooting in production testing: streamlining complexity with high-throughput solutions.
Date and Time
Location
Hosts
Registration
- Date: 25 Jan 2024
- Time: 11:00 AM to 12:00 PM
- All times are (UTC-05:00) Eastern Time (US & Canada)
- Add Event to Calendar
- Contact Event Host
- Co-sponsored by CH01232 - North Jersey Section Chapter,IM09
- Starts 05 January 2024 02:00 PM
- Ends 25 January 2024 12:00 PM
- All times are (UTC-05:00) Eastern Time (US & Canada)
- No Admission Charge
Speakers
Nour Sakhr
Driving 224Gbps System Design with Next-Gen TDR Solutions
Impedance mismatches, skew, and discontinuities at 224Gbps/lane are more pronounced than ever before. Any of these discrepancies can compromise Insertion loss, Signal-to-Noise Ratio (SNR), and contribute to complex troubleshooting, creating much tighter margins for error in System design. Being able to properly account for these constraints will result in a faster time to market for 224Gbps systems.
This MultiLane webinar explores the challenges of host design where tight margins must be considered, and provides an overview of using TDR analysis to accelerate fault detection and troubleshooting in production testing: streamlining complexity with high-throughput solutions.
Biography:
Field Application Engineer, MultiLane
Agenda
Impedance mismatches, skew, and discontinuities at 224Gbps/lane are more pronounced than ever before. Any of these discrepancies can compromise Insertion loss, Signal-to-Noise Ratio (SNR), and contribute to complex troubleshooting, creating much tighter margins for error in System design. Being able to properly account for these constraints will result in a faster time to market for 224Gbps systems.
This MultiLane webinar explores the challenges of host design where tight margins must be considered, and provides an overview of using TDR analysis to accelerate fault detection and troubleshooting in production testing: streamlining complexity with high-throughput solutions.