Dr Zhengya Zhang

Machine learning (ML) is the driving application of the next-generation computational hardware. How to design ML hardware to achieve a high performance, efficiency, and flexibility to support fast growing ML workloads is a key challenge. Besides dataflow-optimized systolic arrays and single instruction, multiple data (SIMD) engines, efficient ML accelerators have been designed to take advantage of static and dynamic data sparsity. To accommodate the fast-evolving ML workloads, matrix engines can be integrated with an FPGA to provide the efficiency of kernel computation and the flexibility of control. To support the increasing ML model complexity, modular chiplets can be tiled on a 2.5D interposer and stacked in a 3D package. We envision that a combination of these techniques will be required to address the needs of future ML applications.

Biography:

Zhengya Zhang received the B.A.Sc. degree from the University of Waterloo in Canada in 2003, and the M.S. and Ph.D. degrees from UC Berkeley in 2005 and 2009. He has been a faculty member at the University of Michigan, Ann Arbor since 2009. His research is in low-power and high-performance integrated circuits and systems for computing, communications, and signal processing. Dr. Zhang was a recipient of the NSF CAREER Award, the Intel Early Career Faculty Award, the Neil Van Eenam Memorial Award from the University of Michigan, and the David J. Sakrison Memorial Prize from UC Berkeley. He served on the program committees of the Symposia on VLSI Technology and Circuits and CICC, and the editorial board of the IEEE Transactions on VLSI Systems.

Email:

Address:University of Michigan, , Ann Arbor, United States