IEEE CTS CAS/SSC Meeting: Ultra low-power analog front-end design


Technical Seminar 

  Date and Time




  • 201 East 24th St
  • Austin, Texas
  • United States 78712
  • Building: POB
  • Room Number: 2.402
  • Click here for Map

Staticmap?size=250x200&sensor=false&zoom=14&markers=30.2868693%2c 97
  • See link to map above. Occasionally you might find street level parking for free -- but watch out for the parking signs and restrictions. Another place to park is SJG, the San Jacinto Garage -- after 6PM, it is $7 to park all night.

  • Starts 19 September 2016 12:00 AM
  • Ends 02 February 2017 12:00 AM
  • All times are US/Central
  • No Admission Charge
  • Register


Pieter Harpe

Pieter Harpe of Eindhoven University of Technology


Ultra low-power analog front-end design


Talk Abstract:

This talk, based on a recent publication, discusses the design of a nano-power analog front-end including pre-amplification and analog-to-digital conversion. It starts with fundamentals on power-efficiency in analog and mixed-signal circuits. It also describes considerations in terms of low-voltage operation and PVT reliability. After that, the presentation discusses one complete system implementation in more detail, including the amplifier, ADC, biasing stages and clock generation.

Speaker Bio:
Pieter Harpe received the M.Sc. and Ph.D. degrees from the Eindhoven University of Technology, The Netherlands. In 2008, he joined Holst Centre / imec where he worked on low-power ADCs. In April 2011, he joined Eindhoven University of Technology as assistant professor on low-power mixed-signal circuits. His main interests include power-efficient and reconfigurable data converters and low-power analog design.


11am: seminar