Verilog HDL & FPGA Design Flow Workshop

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Building blocks for Digital Design Success

The IEEE Student Branch (SB) of Goa College of Engineering (GEC), in collaboration with GEC’s Department of Electronics & Telecommunication Engineering (E&TC), organized a comprehensive 6-day workshop focused on Verilog HDL and FPGA Design Flow.

Key Details:

  • Resource Person: Dr. Nitesh Guinde, Professor, E&TC Engineering, GEC.

  • Student Teaching Assistants: Steven Vazhappully, Amogha Kantak and Mulla Aizaz Muzawar.

  • Duration: Every Saturday for six consecutive weeks, commencing from February 10th, 2024, to March 16th, 2024.

  • Participants: 40 enthusiastic third-year students from the Electronics and Telecommunication Department.

  • Event Support: The workshop was expertly organized with the assistance of dedicated volunteer Meharsh Kubal.

Objectives:

  • Gain proficiency in Verilog HDL fundamentals.

  • Learn to design, simulate, and verify digital circuits.

  • Explore FPGA design flow and optimization strategies.

Workshop Content Covered:

  • Overview of VLSI design flow.

  • Digital IC design and verification with Verilog testbenches.

  • Understanding different design styles (structural, data flow, behavioral).

  • Finite State Machine (FSM) implementation and real-world applications.

  • Counters, delays, and memory design using Verilog.

  • Hands-on experience with FPGA implementation using Xilinx Vivado and Zedboard.

Outcome:

  • Participants can proficiently design and simulate basic digital circuits using Verilog HDL and ModelSim.

  • Strong understanding of FPGA design flow, tools, and techniques.

  • Ability to analyze, debug, and optimize digital circuit designs.

  • Solid foundation in Verilog HDL syntax, data types, operators, and control structures for future projects and learning endeavors.

Additional Highlights:

  • Refreshments were provided to participants after each workshop session.

  • The workshop concluded successfully, and all attendees received certificates in recognition of their participation and dedication.

The workshop served as a valuable learning experience, empowering participants with essential skills and knowledge in digital circuit design and FPGA implementation.

 

 

 

 

 

 

 

 

 


  Date and Time

  Location

  Hosts

  Registration


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  • ETC department, GEC , Farmagudi , Goa
  • Ponda, Goa
  • India
  • Contact Event Host




Agenda

  • Participants can proficiently design and simulate basic digital circuits using Verilog HDL and ModelSim.

  • Strong understanding of FPGA design flow, tools, and techniques.

  • Ability to analyze, debug, and optimize digital circuit designs.

  • Solid foundation in Verilog HDL syntax, data types, operators, and control structures for future projects and learning endeavors.


Unlocking the power of Verilog HDL and FPGA Design: A gateway to Digital Innovation