Forward-Looking Roadmap View to Enable Heterogeneous Integration (HI) in the Next 10 Years.

#Chiplet #heterogeneous #integration # #Advanced #packaging #Thermal #Warpage #wafer #bonding
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IEEE EPS Dallas chapter distinguished lecture from Dr.   Gamal Refai-Ahmed, a senior fellow at AMD.



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  • Date: 28 Mar 2024
  • Time: 09:30 AM to 10:30 AM
  • All times are (UTC-05:00) Central Time (US & Canada)
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  • Co-sponsored by Rajen Murugan
  • Starts 26 March 2024 11:58 PM
  • Ends 28 March 2024 09:00 AM
  • All times are (UTC-05:00) Central Time (US & Canada)
  • No Admission Charge


  Speakers

Gemal of AMD

Topic:

Forward-Looking Roadmap View to Enable Heterogeneous Integration (HI) in the Next 10 Years

The future of heterogeneous integration (HI) with chiplets promises revolutionary advancements, but unlocking its potential requires confronting significant challenges. This talk will navigate the technology's roadmap, shedding light on emerging trends and potential obstacles. Key discussions will center on critical trade-offs affecting package substrates, silicon die size, power density, thermal resistance, package coplanarity, and warpage, and the intricacies of ball-grid array assembly. Understanding these trade-offs is critical for developing thermal solutions that support technological progress through viable thermal and mechanical designs.

Looking ahead to 2033, the shift towards larger die sizes might necessitate a System on Wafer approach to address constraints faced by chiplet-based integration. Successfully navigating this complex landscape demands a collaborative effort between industry and academia. A strategic partnership would drive essential advancements in heterogeneous integration, propelling the technology toward its full potential.

Biography:

Dr. Gamal Refai-Ahmed, a Life Fellow of the American Society of Mechanical Engineers (ASME), Fellow of the Institute of Electrical and Electronics Engineers (IEEE),  Fellow of the Canadian Academy of Engineering, Fellow of the Engineering Institute of Canada and a Member of the National Academy of Engineering (NAE), has led a prolific career spanning over three decades in both industry and academia. Renowned for his pioneering efforts in thermal management, system integration, and advanced packaging, his work has been instrumental in driving innovation and leadership in the engineering domain.

Technical Pioneering: Authored more than 125 publications and holds over 115 US and international patents, influencing advancements across a broad spectrum of fields such as High-Performance Computing (HPC), Artificial Intelligence (AI), Machine Learning (ML), Network Interface Cards (NICs), gaming consoles, aerospace and defense, and telecommunications.

At AMD, he was pivotal in integrating system-level considerations—power, thermal, mechanical, and assembly—within package and silicon development, leading to the launch of high-end silicon GPU and FPGA  packages.

Leadership and Recognition: Dr. Refai-Ahmed's contributions have been acknowledged through prestigious awards, including the ASME Service Award (2016), IEEE Canada R. H. Tanner Industry Leadership Award (2014), and the SUNY Binghamton University Presidential Medal (2019).

His election as a Fellow of ASME, IEEE, EIC, and CAE, and his induction into the NAE, underscore his exceptional impact on the engineering community.

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Agenda

The future of heterogeneous integration (HI) with chiplets promises revolutionary advancements, but unlocking its potential requires confronting significant challenges. This talk will navigate the technology's roadmap, shedding light on emerging trends and potential obstacles. Key discussions will center on critical trade-offs affecting package substrates, silicon die size, power density, thermal resistance, package coplanarity, and warpage, and the intricacies of ball-grid array assembly. Understanding these trade-offs is critical for developing thermal solutions that support technological progress through viable thermal and mechanical designs.

Looking ahead to 2033, the shift towards larger die sizes might necessitate a System on Wafer approach to address constraints faced by chiplet-based integration. Successfully navigating this complex landscape demands a collaborative effort between industry and academia. A strategic partnership would drive essential advancements in heterogeneous integration, propelling the technology toward its full potential.