SILICON TO SYSTEM DESIGN
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This is a Five day National level workshop.
The workshop is organized with industry experts to have the real time experience for the students. This workshop is to explore through silicon to systems design. In this workshop students learn about physical design , road map to semiconductors , digital system design - FPGA , design for testability and design verification of a system. The industrial expert has explained through cadence virtuoso tool. Hands-on-session is provided for effective learning by practitioners.
Atlast we have conducted quiz to students to test how much information did students gained and the outcome is good.
Date and Time
Location
Hosts
Registration
- Start time: 18 Aug 2023 10:00 AM
- End time: 23 Aug 2023 04:30 PM
- All times are (UTC+05:30) Chennai
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- Kurnool, Andhra Pradesh
- India 518002
- Starts 10 August 2023 09:00 AM
- Ends 17 August 2023 09:00 PM
- All times are (UTC+05:30) Chennai
- No Admission Charge
Speakers
Sri P. Sai Krishna
PHYSICAL DESIGN
Biography:
Physical Design engineer, ARM , Bangalore.
Sri Rajesh Sama
Roadmap to semiconductors
Biography:
DFX-DFT Design Engineer, AMD Research and Development Centre India Pvt Ltd, Hyderabad.
K. Lavanya
Digital system design- FPGA
Biography:
Jr. Application Engineer ,Unistring Tech solutions Pvt Ltd, Hyderabad.
Kuruva Veeresh
Design for testability
Biography:
VLSI Design, DFT Engineer L&T Technology Services, Mysore.
N.V. Arun
DESIGN verification
Biography:
solutions engineer ,Synopsys, Bangalore.