Puneet Mittal of VLSI Expert

The work covered..
- Couple of unix command.
- Overview of VLSI Flow
>RTL level Partitions and Floorplan level Partitions
-Hierarchical Design and Flat design
-Power domain, Voltage domain, Clock domain concepts
-Importance of Block level constraints and Top level constraints
>Logic Synthesis Understanding
>Overview of Synthesis Optimisation based on timing constraints.
-Create clock constraint
-Input-output constraint
-Delay (min/max/rise/fall),Transition constraints
>Floor-plan and Powerplan overview
-Utilisation factor, Aspect ration (how we create and why)
-Physical Constraints (pin location)
-Why we have blockages, keep-out margins.
-Power Rings, Power Mesh, Power strips
>Standard Cell Placement concepts
-Concepts of Height, 9/11Track Libraries
-Site Rows concepts
>Clock Routing, Signal Routing
-M1-M8 Layer Stack concepts
-Width, Thickness, Spacing Concept
-Resistance and Capacitance Concepts
-Interconnect Corner concepts
-Routing Tracks, Pitch and design perspective critical wire concepts
>DRC and DFM Concepts
- Input and Output file’s Understanding
-Liberty (.lib) file, SDC, Power constraint, UPF file
-Lef/Def, Spice netlist, verilog netlist, gatelevel netlist
-SDC, SDF, SPEF
-ITF file, Tech file, Tluplus file, Nxtgrd file
Timing Report
- PDK concepts and Synopsys RM flow.
- Static Timing Analysis Concepts and related Lab
-Cell Delay concepts and Delay models (NLDM and CCS model importance and difference)
-PVT corner concepts and RC corners concepts
-Net delay model
-Different delay calculation techniques (GBA and PBA), How tool do the calculation in case of
NLDM models
-Timing ARC, Timing Paths and related Timing Checks.
-DRV checks
-Timing report command and its different switches
- As part of Lab covered
-How tool invoke in GUI and terminal for Design Compiler (DC), ICC2, PrimeTime (PT).
-What are different input files for each stage and why
-What’s the role of Don’t use cells - how it will impact on gate level netlist
-What’s the importance of Clock constraints, input and output put constraints and impact of their
value on design.
-Different floorplan shapes (T, U, L, Rectangle and Square) and impact of physical constants
-How to build power stripes, power rail and power mesh.
-How to do placement of cells and how tool optimise all these as per the given constraints.
-Importance of Metal Stack. Routing of the given design.
-In the last the timing analysis and setup and hold check and its respective reports.

Biography:

Puneet Mittal is Expert at VLSI Expert Pvt. Industry expert and trainer

Email:

Address:Delhi