Feed Your Mind - Practical Aspects of Machine Learning Circuits and Systems
The IEEE Central Texas CASS & SSCS JT. Chapter,
Circuits And Systems Society Outreach Program,
Silicon Laboratories
Present:
Feed Your Mind - Practical Aspects of Machine Learning Circuits and Systems
What is behind the buzzwords Machine Learning, Artificial Intelligence? In this lecture Prof. H. Li and A. Sanyal will present practical aspects applied to circuits and systems solutions for everyday's life.
AI Models for Edge Computing: Hardware-aware Optimizations for Efficiency
Abstract: As artificial intelligence (AI) transforms various industries, state-of-the-art models have exploded in size and capability. The growth in AI model complexity is rapidly outstripping hardware evolution, making the deployment of these models on edge devices remain challenging. To enable advanced AI locally, models must be optimized for fitting into the hardware constraints. In this presentation, we will first discuss how computing hardware designs impact the effectiveness of commonly used AI model optimizations for efficiency, including techniques like quantization and pruning. Additionally, we will present several methods, such as hardware-aware quantization and structured pruning, to demonstrate the significance of software/hardware co-design. We will also demonstrate how these methods can be understood via a straightforward theoretical framework, facilitating their seamless integration in practical applications and their straightforward extension to distributed edge computing. At the conclusion of our presentation, we will share our insights and vision for achieving efficient and robust AI at the edge.
Health management using intelligent wearables with mixed-signal AI
Abstract: As medical wearables become more widely adopted for at-home/early diagnosis/health surveillance, the volume of data produced by these devices are expected to reach thousands of petabytes/month. Transmitting this large volume of data over the cloud for processing will potentially emerge as a communication bottleneck and increase latency of decisions. Transmitting naively all data generated by a wearable medical device is also costly in terms of power/energy- transmitter is usually the highest consumer of energy in a sensor (at least 10~20x more energy than sensing). Key to addressing this data deluge is to increase capabilities of the wearable devices to process information locally and have on-device inference capabilities, such as through embedding AI capabilities into the wearable device that will allow extraction of key information from the sensor data. There needs to be balance between what can be processed locally on-device with low power/energy and how to optimally decide the volume of data communication from the device (to cloud as an example). The barriers to this approach lie in the computational complexity of AI algorithms that makes it challenging to fit AI models on wearables with limited resources. Some of the answers might lie in going back to early days of signal processing in silicon – developing analog circuit techniques for AI development which will require collaborative innovations in both AI model development and analog circuit design techniques. In this talk, I will present our research on developing analog AI circuits and their demonstrations with patient data with use cases from cardiovascular health monitoring and sepsis onset detection.
Date and Time
Location
Hosts
Registration
- Date: 03 Jun 2024
- Time: 10:00 AM to 01:00 PM
- All times are (UTC-05:00) Central Time (US & Canada)
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- 200 W. Cezar Chavez
- Austin, Texas
- United States 78701
- Building: Silicon Labs
- Contact Event Host
- Co-sponsored by Mikko Sojonen - Silicon Labs
- Starts 19 April 2024 12:00 AM
- Ends 03 June 2024 12:00 AM
- All times are (UTC-05:00) Central Time (US & Canada)
- No Admission Charge
Speakers
Helen Li of Duke University
AI Models for Edge Computing: Hardware-aware Optimizations for Efficiency
As artificial intelligence (AI) transforms various industries, state-of-the-art models have exploded in size and capability. The growth in AI model complexity is rapidly outstripping hardware evolution, making the deployment of these models on edge devices remain challenging. To enable advanced AI locally, models must be optimized for fitting into the hardware constraints. In this presentation, we will first discuss how computing hardware designs impact the effectiveness of commonly used AI model optimizations for efficiency, including techniques like quantization and pruning. Additionally, we will present several methods, such as hardware-aware quantization and structured pruning, to demonstrate the significance of software/hardware co-design. We will also demonstrate how these methods can be understood via a straightforward theoretical framework, facilitating their seamless integration in practical applications and their straightforward extension to distributed edge computing. At the conclusion of our presentation, we will share our insights and vision for achieving efficient and robust AI at the edge.
Biography:
Hai “Helen” Li is the Clare Boothe Luce Professor and Department Chair of the Electrical and Computer Engineering Department at Duke University. She received her B.S and M.S. from Tsinghua University and Ph.D. from Purdue University. Her research interests include neuromorphic circuit and system for brain-inspired computing, machine learning acceleration and trustworthy AI, conventional and emerging memory design and architecture, and software and hardware co-design. Dr. Li served/serves as the Associate Editor for multiple IEEE and ACM journals. She was the General Chair or Technical Program Chair of multiple IEEE/ACM conferences and the Technical Program Committee members of over 30 international conference series. Dr. Li is a Distinguished Lecturer of the IEEE CAS society (2018-2019) and a distinguished speaker of ACM (2017-2020). Dr. Li is a recipient of the NSF Career Award, DARPA Young Faculty Award, TUM-IAS Hans Fischer Fellowship from Germany, ELATE Fellowship, nine best paper awards and another nine best paper nominations. Dr. Li is a fellow of ACM and IEEE.
Address:United States
Arindam Sanyal
Health management using intelligent wearables with mixed-signal AI
As medical wearables become more widely adopted for at-home/early diagnosis/health surveillance, the volume of data produced by these devices are expected to reach thousands of petabytes/month. Transmitting this large volume of data over the cloud for processing will potentially emerge as a communication bottleneck and increase latency of decisions. Transmitting naively all data generated by a wearable medical device is also costly in terms of power/energy- transmitter is usually the highest consumer of energy in a sensor (at least 10~20x more energy than sensing). Key to addressing this data deluge is to increase capabilities of the wearable devices to process information locally and have on-device inference capabilities, such as through embedding AI capabilities into the wearable device that will allow extraction of key information from the sensor data. There needs to be balance between what can be processed locally on-device with low power/energy and how to optimally decide the volume of data communication from the device (to cloud as an example). The barriers to this approach lie in the computational complexity of AI algorithms that makes it challenging to fit AI models on wearables with limited resources. Some of the answers might lie in going back to early days of signal processing in silicon – developing analog circuit techniques for AI development which will require collaborative innovations in both AI model development and analog circuit design techniques. In this talk, I will present our research on developing analog AI circuits and their demonstrations with patient data with use cases from cardiovascular health monitoring and sepsis onset detection.
Biography:
Bio: Arindam Sanyal is currently an assistant professor in the School of Electrical, Computer and Energy Engineering at Arizona State University. Prior to this, he was an analog design engineer with Silicon Laboratories and assistant professor in State University of New York. He received his PhD in Electrical and Computer Engineering from the University of Texas at Austin in 2015, his M.Tech from The Indian Institute of Technology, Kharagpur in 2009 and B.E from Jadavpur University, India in 2007. Dr. Sanyal’s research expertise includes analog/mixed signal design, bio-medical sensor design, hardware security and neuromorphic computing.
Address:United States
Agenda
Program:
- Introduction Dr. S. Pietri (NXP) and J. Elenes (Silabs)= 10 – 10:15 am
- Dr. Hai "Helen" Li (Duke University) lecture= 10-11:15 am
- Break= 11:15 – 11:45 am (chapter will provide pizza and soda)
- Dr. Arindam Sanyal (Arizona State University) lecture= 11:45 – 1:00pm