Training for students and professionals in "RISC V comprehensive course - architecture and programming"

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Its a training program for the students and professionals of Cambridge Institute of Technology, completely sponsored by the Management of Cambridge Institute of Technology. 

Target Audience: Undergraduate, Postgraduate, and Faculty from Departments including CSE, ISE, AI/ML, ECE, EEE, MCA, and MTECH

About RISC V:

RISC-V is an open-source instruction set architecture (ISA) designed to be simple, modular, and extensible. It offers a flexible framework for designing processors suitable for a wide range of applications, from embedded systems to supercomputers. RISC-V is gaining popularity due to its open nature, enabling innovation, collaboration, and customization in the processor design space.

Phase-1 Syllabus Includes:
• Introduction to RISC-V Architecture
• RISC-V Pipeline Architecture
• Assembly Language Programming
• Spike Simulator
• Advanced Assembly Language Programming
• Implementing on FPGA & Bare Metal Programming
• Bare Metal Programming in RUST

Exciting Incentives Awaits:
•  Cash Awards: The top 2 performers at AARFIVE Academy will be awarded Rs. 100,000/ each!
•  Internship & Job Placement: Top performers will have access to rich internship opportunities and job placements based on merit.
•  Further Academic Opportunities: Selected students will be recommended for Doctorate and Post-Doc programs at esteemed institutions.


  Date and Time

  Location

  Hosts

  Registration


  • Start time: 12 Apr 2024 01:10 AM
  • End time: 25 Jun 2024 01:10 AM
  • All times are (UTC+05:30) Chennai
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  • Cambridge Institute of Technology, Jai Bhuvaneshwari Nagar
  • Near T C Palya signal, K R Puram
  • Bangalore, Karnataka
  • India 560036
  • Building: Department of ECE, Sir M V Block
  • Room Number: Centre of excellence for semiconductors
  • Contact Event Host
  • Co-sponsored by AARFIVE Pvt Ltd
  • Starts 16 March 2024 12:00 AM
  • Ends 16 April 2024 01:41 AM
  • All times are (UTC+05:30) Chennai
  • No Admission Charge

  Speakers

Dr Sujay Deb of Indraprastha Institute of Information Technology, Delhi (IIIT-D)

Biography:

Sujay Deb is a Professor in Electronics & Communication Engineering and Computer Science & Engineering at Indraprastha Institute of Information Technology, Delhi (IIIT-D). He received Ph.D. from the School of Electrical Engineering and Computer Science, Washington State University, Pullman, WA on May 2012. Before his current position, he worked as an intern at Intel Labs, Hillsboro, OR. His major awards and achievements include DST INSPIRE Faculty award in 2012; Outstanding Ph.D. student award in Computer Engineering, WSU, 2011; Winner of India-US Grand Challenge Initiative for Affordable Blood Pressure measurement technologies in 2014.

Address: Indraprastha Institute of Information Technology, Delhi (IIIT-D), , Delhi, India

Subhra Das of Head of Department, Research Technology and Innovation @ Thales

Topic:

RISC V

Biography:

Subhra Das, based in Bengaluru, KA, IN, is currently a Head of Department, Research Technology and Innovation at Thales, bringing experience from previous roles at Thales, University of Southampton and Collins Aerospace. Subhra Das holds a 2011 - 2016 Doctor of Philosophy - PhD in Computer Engineering @ Jadavpur University. With a robust skill set that includes Simulations, C, Statistical Modeling, Algorithms, Machine Learning and more, Subhra Das contributes valuable insights to the industry. Subhra Das has 1 mobile phone number on RocketReach.

Address:Bangalore, India





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