Extending and Augmenting Analog with Digital to Overcome Technology Scaling Limitations

#Analog #DigitalAssisted #SSCS #IEEE #TechnologyScaling #CMOS #Tech
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ABSTRACT
Embrace the technology – the essence of how analog design has adapted and thrived throughout decades of increasingly unfriendly CMOS scaling.  This presentation will cover the evolution of CMOS technology, its impact on analog design, and examples of the creativity of analog designers to preserve and extend the performance of traditional analog functions.  We will finally take a look at technologies on the horizon and suggest how they will impact the future of analog design.

Online webinar link: https://zoom.us/j/95018761168



  Date and Time

  Location

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  • Date: 17 May 2024
  • Time: 02:00 PM to 05:00 PM
  • All times are (UTC+01:00) Dublin
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  • Tyndall National Institute, Lee Maltings Complex Dyke Parade
  • cork, Cork
  • Ireland T12 R5CP
  • Building: BLOCK B
  • Room Number: B.0.17
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  • Starts 27 April 2024 12:00 AM
  • Ends 17 May 2024 12:00 AM
  • All times are (UTC+01:00) Dublin
  • No Admission Charge


  Speakers

Alvin Loke of Intel

Topic:

Extending and Augmenting Analog with Digital to Overcome Technology Scaling Limitations

Embrace the technology – the essence of how analog design has adapted and thrived throughout decades of increasingly unfriendly CMOS scaling.  This presentation will cover the evolution of CMOS technology, its impact on analog design, and examples of the creativity of analog designers to preserve and extend the performance of traditional analog functions.  We will finally take a look at technologies on the horizon and suggest how they will impact the future of analog design.

Biography:

Alvin Loke recently joined Intel as a Senior Principal Engineer in the area of analog design/technology co-optimization for Intel's most advanced process technologies.  He received his Ph.D. in electrical engineering from Stanford University in 1999 and has previously worked on every CMOS node from 250nm to 2nm.  His experience covers CMOS process integration to analog/mixed-signal and wireline design as well as design/model/technology interfacing.  He has previously worked at Agilent Technologies, AMD, Qualcomm, TSMC and most recently NXP Semiconductors.  Since 2003, Alvin has served multiple roles in the IEEE Solid-State Circuits Society including Distinguished Lecturer, AdCom Member, Denver and San Diego Chapter Chiar, JSSC/EDL/SSC-Magazine Guest Editor, Webinar Chair, and currently Chapters Chair and Publicity Chair of the VLSI Symposium.

Email:

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