Bridging the gap - From Noisy Memristive Devices to Reliable AI Accelerators
As the complexity of AI models continues to soar, so does the energy required for their training and inference operations. Additionally, these models frequently create unreliable outcomes due to their inability to address uncertainty inherent in both the models themselves and the data they operate on. To combat these challenges, researchers have turned their attention to alternative approaches, with a particular focus on leveraging low-power nanoscale devices and brain-inspired computing architectures.
Yet, transitioning to the nanoscale realm presents its own set of hurdles. Noise, a persistent issue in digital CMOS technology, becomes even more pronounced at the nanoscale, posing a significant barrier to achieving reliable and efficient AI accelerators.
In this talk, I will discuss our recent results focusing on the utilization of nanoscale devices to create efficient and reliable AI accelerators. Our strategy revolves around two primary pillars: firstly, implementing architectural techniques to mitigate the adverse effects of device noise, which can enable deep learning accelerators that outperform their digital counterparts by over 100-fold in efficiency; and secondly, harnessing the stochastic nature of nanoscale devices to realize Bayesian AI models in hardware. These hardware accelerators can efficiently generate quantifiable metrics of uncertainty, potentially enhancing the reliability of AI-based decision-making processes and systems.
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- Level 11
- Singapore, Singapore
- Singapore 138632
- Building: Connexis South Tower
- Room Number: Franklin Room
- Starts 14 May 2024 04:00 PM UTC
- Ends 22 May 2024 04:00 PM UTC
- No Admission Charge