Sorin of Delft University of Technology

In this presentation we provide an overview of recent efforts to develop computing systems based on spin waves instead of charges and voltages. Note that Spin-wave computing can be considered a subfield of spintronics, which uses magnetic excitations for computation and memory applications. We start with an introduction to magnetic interactions, spin-wave physics, and basic spin-wave computing mechanisms. Subsequently, we review individual spin-wave devices while focusing on spin-wave majority gates as they are the most prominently pursued spin-wave device concept. Afterwards, we discuss the state-of-the-art and the challenges to combine spin-wave gates to obtain circuits and ultimately computing systems, by considering essential aspects, e.g., gate interconnection, logic level restoration, input-output consistency, and fan-out achievement. Then, we argue that spin-wave circuits need to be embedded into conventional complementary metal-oxide-semiconductor (CMOS) circuits to obtain complete functional hybrid computing systems and discus the potential performance of such hybrid spin-wave-CMOS systems and challenges towards their practical realization. Our estimates indicate that hybrid spin-wave-CMOS systems exhibit ultralow-power operation and may ultimately outperform conventional CMOS circuits in terms of power-delay-area product. Finally, we briefly present the SPIDER project (EC contract number 101070417) approach, which is the first ever attempt to experimentally demonstrate the feasibility of hybrid spin-wave-CMOS systems.

Biography:

Sorin Cotofana received the MSc degree in Computer Science from the "Politechnica" University of Bucharest, Romania, and the PhD degree in Electrical Engineering from Delft University of Technology, The Netherlands. He is currently with the Electrical Engineering, Mathematics and Computer Science Faculty, Delft University of Technology, Delft, the Netherlands. His current research is focused on: (i) the design and implementation of dependable/reliable systems out of unpredictable/unreliable components; (ii) ageing assessment/prediction and lifetime reliability aware resource management; and (iii) unconventional computation paradigms and computation with emerging nano-devices. He (co-)authored more than 300 papers in peer-reviewed international journal and conferences, and received 12 international conferences best paper awards, e.g., 2012 IEEE Conference on Nanotechnology, 2012 ACM/IEEE International Symposium on Nanoscale Architectures, 2005 IEEE Conference on Nanotechnology, 2001 International Conference on Computer Design. He served as Associate editor for IEEE Transactions on CAS I (2009-2011), IEEE Transactions on Nanotechnology (2008-2014), member of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems Senior Editorial Board (2016-2017), Steering Committee member for IEEE Transactions on Multi-Scale Computing Systems (2014-2018), Chair of the Giga-Nano IEEE CASS Technical Committee (2013-2015), IEEE Nano Council CASS representative (2013-2014), Associate Editor for IEEE Transactions on Computers (2019-2022), CASS Distinguished Lecturer (2019-2022), and has been actively involved as Reviewer, Technical Program Committee (TPC) member, and TPC (track) and general (co)-chair, in the organization of numerous international conferences. He is currently Editor in Chief for IEEE Transactions on Nanotechnology and CAS Board of Governors member (second mandate). He is a Fellow IEEE member (Circuits and System Society (CASS) and Computer Society).

Email:

Address:Delft, Netherlands