IEEE PELS Day - Technical Seminar
Event Description:
Join us in celebrating PELS Day on June 29th, marking the anniversary of the Power Electronics Society (PELS) becoming a full-fledged Society within IEEE in 1987. This special day is an opportunity to gather with colleagues for an afternoon of technical discussions, insightful presentations, and networking.
Agenda:
- 1:00 PM - 1:15 PM: Welcome and Registration
- Begin the event with a warm welcome and registration process. Meet fellow attendees and get ready for an afternoon of learning and networking.
- 1:15 PM - 1:30 PM: Lunch
- Enjoy a light lunch while mingling with colleagues and listening to the technical seminar.
- 1:30 PM - 2:30 PM: Technical Seminar by Kishan Joshi
- Kishan Joshi, a distinguished expert in power electronics, will deliver a seminar titled "Ultra Wideband Low Supply Noise Voltage Regulators and Ripple Suppression Techniques." The talk will cover high power supply rejection over a wide frequency band, a critical requirement for power regulators operating over increasingly higher bandwidths. Kishan will discuss improving power supply rejection (PSR) in linear regulators without increasing power consumption and introduce commercial off-the-shelf (COTS) ripple cancellation systems that work with existing switching regulators to suppress output ripple. His extensive experience in both industry and academia promises valuable insights for professionals and enthusiasts alike.
Don't miss this chance to celebrate the rich history of PELS and contribute to its vibrant community. Whether you are deeply involved in power electronics or just starting out, PELS Day is the perfect occasion to connect, learn, and grow.
RSVP: Please confirm your attendance to ensure we have adequate arrangements for lunch.
We look forward to celebrating PELS Day with you!
The map below will help you locate the engineering center. ECEE 1B32 is in the basement of this building. The nearest parking lot to the entrance gate of the Engineering Center is LOT 444.
https://maps.app.goo.gl/HLZ9GCr7fEs79ruNA
Date and Time
Location
Hosts
Registration
- Date: 29 Jun 2024
- Time: 01:00 PM to 02:30 PM
- All times are (UTC-06:00) Mountain Time (US & Canada)
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- Starts 13 June 2024 12:00 AM
- Ends 29 June 2024 12:00 AM
- All times are (UTC-06:00) Mountain Time (US & Canada)
- No Admission Charge
Speakers
Dr. Kishan Joshi
Ultra wideband low supply noise voltage regulators and ripple suppression techniques
High power supply rejection over a wide frequency band is becoming a critical requirement for power regulators operating over increasingly higher bandwidths. With switching regulators shrinking in size and form factor, the reduction in passive filter sizes is further pushing operating frequencies higher in SoCs. Degraded power supply rejection in conventional linear and switching regulators and consequently higher ripple in the output supply domains these generate have the detrimental effect of impacting down-the-line blocks these regulators power. This manifests as limitation in the linearity of Analog-Digital converters, increased jitter in phase-locked loops which impacts overall SoC performance.
This talk will cover two aspects of improving robustness of supply regulator to power supple ripple. The first part of the talk focuses on improving the power supply rejection (PSR) in a linear regulator which provides good PSR over a wide bandwidth. The talk will cover techniques to improve PSR without increasing the overhead on power consumption in the system. The second part of the talk will address commercial off-the-shelf (COTS) ripple cancellation system that can be used in conjunction with an existing switching regulator to suppress the ripple on the output of the system.
Biography:
Kishan Joshi received his M.S. & Ph.D. degrees in electrical engineering from Arizona State University, Tempe, AZ, USA in 2016 & 2020. He is currently working as an Analog Engineering Manager at Intel Corp., Santa Clara, CA on fully integrated voltage regulators.
Prior to joining Intel, Kishan has worked at Texas Instruments Inc. Tucson, AZ in the Linear Power group designing Low DropOut regulators from 2019 to 2021. He was an analog design intern at Kilby Labs, Texas Instruments, Santa Clara, CA in 2016, at NXP Semiconductors, Chandler, AZ in 2017 and at Linear power group, Texas Instruments, Tucson, AZ in 2018 where he worked on power converters, analog-to-digital converters and ultra-low Iq LDOs respectively. From 2012 to 2014 he was a Digital Circuit Designer at Sankalp Semiconductors Pvt. Ltd., India where he worked on standard cell library design for mixed-signal libraries. His current research interests include low-power analog design, supply ripple rejection and power management IC design. He is a peer reviewer for IEEE Access, TCAS-I & II, TPEL, APEC, ISCAS. From 2022-2024 he has been serving as the Chair of San Francisco Bay Area Council PELS Chapter. He is currently serving as the Regional Chair for IEEE PELS Region 4-6 overseeing ~40 chapters. He is also a member of the PELS TC-10 on design methodologies. He is also the webmaster for the MTT-15 technical committee.