IEEE CTS CAS/SSC Meeting: Phase-Locked Frequency Synthesis and Modulation for Modern Wireless Transceivers


Techinal Seminar by IEEE SSC DL

  Date and Time




  • Date: 04 May 2017
  • Time: 10:00 AM to 11:00 AM
  • All times are (GMT-06:00) US/Central
  • Add_To_Calendar_icon Add Event to Calendar
  • 201 East 24th St
  • Austin, Texas
  • United States 78712
  • Building: POB
  • Room Number: 2.402
  • Click here for Map

  • See link to map above. Occasionally you might find street level parking for free -- but watch out for the parking signs and restrictions. Another place to park is SJG, the San Jacinto Garage -- after 6PM, it is $7 to park all night.

  • Starts 16 December 2016 12:00 AM
  • Ends 04 May 2017 12:00 AM
  • All times are (GMT-06:00) US/Central
  • No Admission Charge


Woogeun Rhee Woogeun Rhee


Phase-Locked Frequency Synthesis and Modulation for Modern Wireless Transceivers

Frequency synthesis and modulation by the DS fractional-N PLL are essential in modern wireless transceivers. In addition to loop parameter variability, leakage current, and matching problems, the DS fractional-N PLL needs to deal with quantization noise and nonlinearity in consideration of phase noise, spur, and settling time. In this talk, various fractional-N PLL architectures (analog/digital/hybrid) and recent circuit techniques for mitigating quantization and nonlinearity will be presented. Also, PLL-based modulation methods (1-point/2-point/2+-point) will be discussed. 


Woogeun Rhee received the B.S. degree in electronics engineering from Seoul National University, Seoul, Korea, in 1991, the M.S. degree in electrical engineering from the University of California, Los Angeles, in 1993, and the Ph.D. degree in electrical and computer engineering from the University of Illinois, Urbana-Champaign, in 2001. From 1997 to 2001, he was with Conexant Systems, Newport Beach, CA, where he was a Principal Engineer and developed low-power, low-cost fractional-N synthesizers. From 2001 to 2006, he was with IBM Thomas J. Watson Research Center, Yorktown Heights, NY and worked on clocking area for high-speed I/O serial links, including low-jitter phase-locked loops, clock-and-data recovery circuits, and on-chip testability circuits. In August 2006, he joined the faculty as an Associate Professor at the Institute of Microelectronics, Tsinghua University, Beijing, China, and became a Professor in December 2011. His current research interests include short-range low-power radios for next generation wireless systems and clock/frequency generation circuits for wireline and wireless communications. He holds 23 U.S. patents. Dr. Rhee is currently an IEEE Distinguished Lecturer of the Solid-State Circuits Society (2016-2017) and serves as an Associate Editor for IEEE JSSC. He has been an Associate Editor for IEEE TCAS-II (2008-2009) and a Guest Editor for IEEE JSSC Special Issue in November 2012 and November 2013. He has served as a member of several IEEE conferences, including ISSCC (2012-2016), CICC, and A-SSCC. He was the co-recipient of the “Silkroad Award” at the 2008 IEEE ISSCC, the “Best Student Paper Award” at the 2012 IEEE RFIT, and the “Best Paper Award” at the 2014 VLSI-DAT. He was the recipient of the “IBM Faculty Award” in 2007 and the “Advanced Employee Award” from Tsinghua University in 2012, and has been listed in “Marquis Who’s Who in the World” since 2009.

Woogeun Rhee


Phase-Locked Frequency Synthesis and Modulation for Modern Wireless Transceivers



10.00am: seminar by DL