CANELOS 2024
No te pierdas la segunda iteración de CANELOS, un seminario que busca ser un punto de reunión de la industria y academia relacionada al maravilloso mundo de la microelectrónica
CANELOS es un seminario enfocado en la amplia gamma de conocimiento e industria centrada en la microelectrónica, abordando temas desde el diseño asistido por computadora (CAD) para circuitos integrados hasta el estado de arte de la tecnología. Este evento será realizado durante los días 3 y 4 de Octubre desde las 9.00 hasta las 18.00 horas, en la Universidad Técnica Federico Santa María ubicada en el Cerro Placeres de la ciudadde Valparaíso. Durante estos 2 días habrán presentaciones de empresa y de centros de investigación, charlas plenarias y un foro de Cierre.
El evento es abierto al público y busca ser el punto en el que la industria y la academia relacionada a la microelectrónica convergen para presentar lo extenso y amplio que es el mundo de la microelectrónica. Es por esto mismo que el evento cumple la función de ser una instancia educativa a la vez de ofrecer la oportunidad de generar contactos con académicos y profesionales Chilenos y del extranjero.
Date and Time
Location
Hosts
Registration
- Start time: 03 Oct 2024 09:00 AM
- End time: 04 Oct 2024 06:30 PM
- All times are (UTC-03:00) Santiago
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- Av. España 1680, Valparaíso
- Valparaiso, Valparaiso
- Chile 2340000
- Building: Edificio T
- Room Number: Auditorio
- Contact Event Hosts
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Si tienen consultas no duden en contactarnos a nuestro correo😄!!
directiva.chipusm@gmail.com
Speakers
Edmundo Gutierrez of INAOE
Desde la escala nano/micro-métrica de los semiconductores a la escala de años luz
Se hace una descripción de los materiales y dispositivos semiconductores en la escala de los micrómetros y nanómetros (unas cuantas capas atómicas), y su uso en la observación y descubrimiento de objetos del tamaño de las galaxias y los agujeros negros en la escala de los años luz. Se muestra que dispositivos semiconductores de escala de unas cuantas capas atómicas son necesarios para observar objetos tan grandes y lejanos en la escala de los años luz.
Biography:
Got his PhD in 1993 from the Catholic University of Leuven, Belgium with the thesis entitled “Electrical performance of submicron CMOS technologies from 300 K to 4.2 K”. From 1989 to 1993, while working for his PhD, served as a research assistant at the Interuniversity Microelectronics Center (IMEC) in Leuven, Belgium. In 1996 was guest Professor at Simon Fraser University, Vancouver, Canada. In 1996 spent two months as an invited lecturer at the Sao Paulo University, Brazil. In 2000 acted as Design Manager of the Motorola Mexico Center for Semiconductor Technology. In 2002 was invited lecturer at the Technical University of Vienna, Austria. In 2005 joined the Intel Mexico Research Center as technical Director. Currently he holds a Professor position at the National Institute for Astrophysics, Optics and Electronics (INAOE), in Puebla, Mexico. Prof. Gutiérrez-D. is an IEEE senior member since 2008.
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Martin Andraud of UCLouvain, Aalto University
Accelerating AI with Compute-In-Memory architectures: a system's view on design, test and reliability aspects
Witnessing the constantly increasing need for energy-efficient computation of Artificial Intelligence (AI) tasks is straightforward today. Whether these computations happen in servers (i.e., on the cloud) or in devices themselves (i.e., on the edge), the situation has started to raise sustainability concerns, requiring significantly more efficient computing technologies for AI. Among promising architectures to accelerate AI tasks on hardware, Compute-In-Memory (CIM) architectures promise orders of magnitude more efficient computation by drastically reducing costly data transfers. To achieve this, CIM can rely on analog computing principles and the massive developments around emerging Non-Volatile Memory (eNVM) technologies. However, designing and deploying efficient and reliable CIM architectures remains a crucial challenge to enable the next generation of computing devices. In this talk, we will start by explaining the main principle of hardware AI acceleration, from generic processors to dedicated AI accelerators. We will then introduce the design of CIM accelerators, covering both digital and mixed-signal aspects. We will draw a possible roadmap for the future of CIM devices, mainly focusing on analog computing with eNVMs. Finally, we will detail several challenges ahead from a system's perspective, in terms of design, test and reliability.
Biography:
Martin Andraud is an assistant professor in microelectronics at UCLouvain, Belgium, and a visiting professor at Aalto University, Finland. He received his PhD from Grenoble University, France, in 2016. He was a postdoctoral researcher successively with TU Eindhoven in 2016 and KU Leuven from 2017 to 2019. Between 2019 and 2024, he was an assistant professor at Aalto University, Finland. His research interests include the interface between edge AI, hardware/software co-design, testing, and reliability of custom ASICs for AI accelerators (for instance, mixed-signal Compute-In-Memory architectures).
Alfonso Chacon of Rydev
Towards an IC design ecosystem in Latin America: what do we need to open an ASIC design house in the region?
The microelectronics industry increasingly depends on the input of multiple suppliers in the area of design and generation of intellectual property (IP). In the last decade, this led to a boom in these design houses in countries in Eastern Europe, Southeast Asia and the Near East. But political realignments, added to the growing complexity of modern chips and the orientation of countries like India towards their internal market, have put the issue of near-shoring back on the table for the North American semiconductor industry. In particular, the growing need for time alignment, and the search for higher quality of remote design services independent of the price factor (increasingly leveled globally anyway). All this implies a magnificent opportunity for more ASIC design houses to appear in Latin America. But the challenge is great: how to quickly generate the necessary critical mass for a successful business? Among the biggest obstacles we face are: very weak electrical or electronic engineering study programs in the area of microelectronics, very few graduate students in areas related to VLSI, the excessive cost of EDA tools for a small company that want to develop its own IP, the lack of a layer of experienced engineers that can guide the design teams, and the industry's lack of knowledge about the existing capabilities in Latin America (lack of positioning). This talk aims to offer
proposals for solutions, based on our own success story at Rydev, a Latin American ASIC design house with operations in Costa Rica and Argentina, that may help motivate more companies to appear in the short term in the region.
Biography:
Born in San José, Costa Rica, in 1967, Alfonso Chacón-Rodriguez holds a Bachelor's degree in Electronics Engineering from the Instituto Tecnológico de Costa Rica (1990), and a Doctorate in Engineering from the Universidad Nacional de Mar del Plata, Argentina (2009). He also holds a Magister Literarum in English Literature from the University of Costa Rica (2004). He has published several papers on digital acoustic signal processing, and has served as reviewer for several IEEE conferences and journals such as the IEEE Sensors Journal, the IEEE Transactions on Circuits and Systems II: Express Briefs, and Springer's Analog Integrated Circuits and Signal Processing. He shared the 2011 National Literature Award in his country for his novel El luto de la libélula. His interests range from low power analog and digital VLSI, low power signal processing and digital systems architecture, to philosophy and literature. He's co-founder and VP of Business Development at Rydev ASIC Design House, since 2021.
Media
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