Dr. Vincenzo Piuri of Università degli Studi di Milano, Italy

Die-stacked 3D DRAM technology can provide low-energy high-bandwidth memory module by vertically integrating several dies within the same chip. However, the size of such 3D memory is unlikely to be sufficient to provide the full memory capacity, so future memory systems are likely to use 3D DRAM together with traditional off-chip DRAM. In-fact, such systems are already being announced by the industry. This talk will discuss our work on architecting DRAM caches and share some of the insights and experiences that run counter to the well-established conventional wisdom in cache design. It will be shown that some of the basic design decisions typically made for conventional caches (such as serialization of tag and data access, large associativity, and update of replacement state) are detrimental to the performance of DRAM caches, as they increase the hit latency. The talk will present Alloy Cache, a simple latency-optimized DRAM cache design that can outperform even an impractical SRAM tag-store design, which would incur an unacceptable overhead of several tens of megabytes. The talk will also present our CAMEO architecture that allows “Gigascale” DRAM caches to not only be transparently managed by the hardware but also to contribute to the OS-visible main-memory capacity. The talk will then analyze the bandwidth consumed by management operations (miss detection, install, write-backs etc.), show that these operations consume as much as 3x the cache bandwidth compared to the bandwidth consumed by data transfer on a cache hit, and present simple solutions to mitigate this bandwidth bloat. If time permits, the talk will also briefly discuss schemes that can proactively reduce the DRAM cache hit-rate to improve overall system performance.

Biography:

Vincenzo PIURI hasreceived his Ph.D. in computer engineering at Politecnico di Milano, Italy (1989). He has been Associate Professor at Politecnico di Milano, Italy and Visiting Professor at the University of Texas at Austin and at George Mason University, USA. He is Full Professor in computer engineering at the Università degli Studi di Milano, Italy (since 2000).

His main research interests are: signal and image processing, biometrics, machine learning, pattern analysis and recognition. Original results have been published in more than 350 papers in international journals, proceedings of international conferences, books, and book chapters.

He is Fellow of the IEEE, Distinguished Scientist of ACM, and Senior Member of INNS. He is IEEE Past Vice President for Technical Activities, IEEE Director. He is Editor-in-Chief of the IEEE Systems Journal (2013-17).

Email:

Address:Computer Engineering Department, Università degli Studi di Milano, Italy, Milano, Italy

Dr. Vincenzo Piuri of Università degli Studi di Milano, Italy

Biography:

Email:

Address:Milano, Italy

Dr. Vincenzo Piuri of Università degli Studi di Milano, Italy

Biography:

Email:

Address:Milano, Italy