EPS Nordic Chapter Seminar: Software engineering and formal methods for improved chip design productivity
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EPS Nordic Chapter Seminar given by Mr. Edward Wang from MIT Diverse applications from medical devices to machine learning demand specialized chips for improved performance, energy efficiency and reliability. Despite over two decades of chip design activity, the cost of designing new chips remains stubbornly high. Agile development methods show great promise in software engineering, enabling small teams to produce higher quality software faster. Unfortunately, adapting agile methods to hardware remains challenging. Inadequately reliable and re-usable tooling leads to lack of re-use and single-use effort, resulting in long incremental cycles which hamper the adoption of agile methods in hardware design. In this talk, I will discuss two tools that I have developed to address these challenges. The first tool addresses the challenge of re-use by modularizing the chip design process using plugins, facilitating intermixing of distinct pieces of information. This allows distinct chip projects to collaborate and share effort, significantly reducing design time and increasing the overall efficiency of chip design projects. The second tool addresses the challenge of single-use effort by employing formal methods and SMT to drive a correctness-first approach to place-and-route, a key step in the chip design process. By producing defect-free designs by construction, designer time spent on single-cycle efforts can be reduced, empowering agile methods. |
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Mr. Edward Wang
Software engineering and formal methods for improved chip design productivity
Diverse applications from medical devices to machine learning demand specialized chips for improved performance, energy efficiency and
reliability. Despite over two decades of chip design activity, the cost of designing new chips remains stubbornly high. Agile development
methods show great promise in software engineering, enabling small teams to produce higher quality software faster. Unfortunately,
adapting agile methods to hardware remains challenging. Inadequately reliable and re-usable tooling leads to lack of re-use and single-use
effort, resulting in long incremental cycles which hamper the adoption of agile methods in hardware design. In this talk, I will discuss two tools that I have developed to address these challenges.
The first tool addresses the challenge of re-use by modularizing the chip design process using plugins, facilitating intermixing of
distinct pieces of information. This allows distinct chip projects to collaborate and share effort, significantly reducing design time and
increasing the overall efficiency of chip design projects. The second tool addresses the challenge of single-use effort by employing formal
methods and SMT to drive a correctness-first approach to place-and-route, a key step in the chip design process. By producing defect-free designs by construction, designer time spent on single-cycle efforts can be reduced, empowering agile methods.
Biography:
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Edward Wang is a PhD candidate in EECS at the Massachusetts Institute of Technology. He obtained his B.S. and M.S. degrees in EECS from the University of California, Berkeley, in 2017 and 2018, respectively. His research interests include formal methods, artificial intelligence (AI), electronic design automation (EDA), computer-aided design (CAD), and compilers. His passion is to enable the design of larger and more complex systems that are both correct and secure by developing innovative tools. His work has been showcased at conferences such as DAC, ISQED, and EMSOFT. |
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Address:Cambridge, , Massachusetts, United States