High-Level Synthesis Based Hardware Security and IP Core Protection (IPP)

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This talk presents a novel taxonomy of high level synthesis (HLS) based hardware security approaches for reusable intellectual property (IP) cores used in consumer electronics and computing systems. A succinct review of some of major HLS based hardware security approaches applied on reusable IP cores, along with their design flow and security analysis, is provided. The talk also presents a detailed design flow of hardware integrated circuits (ICs) along with vulnerability points where potential attacks/threats are possible. Trustworthy and untrustworthy regimes in the design flow have also been highlighted in the discussion. Further, a discussion of detective and preventive control-based HLS hardware security approaches used for hardware IP cores has also been presented.



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  • Vinit Kumar Gunjan, Ph.D.
    Chair IEEE Computer Society and Additional Treasurer 2024
    IEEE Hyderabad Section
    No: 644-645Al-Karim Trade Center,
    Ranigunj,Secunderabad – 500 003.
    Telangana. India.
    Ph:- +91-9441328438

  • Starts 26 September 2024 04:30 PM UTC
  • Ends 03 October 2024 06:30 PM UTC
  • No Admission Charge


  Speakers

PROF. ANIRBAN SENGUPTA of Indian Institute of Technology, Indore, India

Topic:

High-Level Synthesis Based Hardware Security and IP Core Protection (IPP)

This talk presents a novel taxonomy of high level synthesis (HLS) based hardware security approaches for reusable intellectual property (IP) cores used in consumer electronics and computing systems. A succinct review of some of major HLS based hardware security approaches applied on reusable IP cores, along with their design flow and security analysis, is provided. The talk also presents a detailed design flow of hardware integrated circuits (ICs) along with vulnerability points where potential attacks/threats are possible. Trustworthy and untrustworthy regimes in the design flow have also been highlighted in the discussion. Further, a discussion of detective and preventive control-based HLS hardware security approaches used for hardware IP cores has also been presented.

Biography:

Prof. Anirban Sengupta (FIET, FBCS, FIETE, Ph.D.) is a full Professor in the Department of Computer Science and Engineering at Indian Institute of Technology (IIT) Indore. He has more than 321 publications and patents, including 6 books published from England, to his credit. He has 13 patents in India, USA and Canada, some of which are commercialized to VLSI-CAD industries. He is the Editor-in-Chief of IET Computers and Digital Techniques, which is a sixty year old well-known British Journal in the area of CAD-VLSI.

His is recipient of awards/honors such as Fellow of IET, Fellow of British Computer Society, Fellow of IETE, IEEE Chester Sall Memorial Consumer Electronics Award, IEEE Distinguished Lecturer of IEEE Consumer Technology Society, IEEE Distinguished Visitor of IEEE Computer Society, IEEE CESoc Outstanding Editor Award, IEEE CESoc Best Research Award from CEM, Best Research paper Award in IEEE ICCE 2019, IEEE Computer Society TCVLSI Outstanding Editor Award and IEEE TCVLSI Best Paper Award in IEEE iNIS 2017. He held/holds around 20 Editorial positions in IEEE, Nature, IET Journal boards. He has been chair of IEEE Computer Society Technical Committee on VLSI, IEEE Consumer Technology Society Technical Committee on Security and Privacy and Chair of IEEE Consumer Technology Society Madhya Pradesh Chapter. He is consistently ranked in Stanford University’s Top 2 % Scientists globally for last 4 years (both in terms of career long impact and single recent year performance) and has more than 3000 citations as per G-Scholar.

Details available at: http://www.anirban-sengupta.com/index.php

 

 

 

 

Email:

Address:Department of Computer Science and Engineering, Indian Institute of Technology, Indore, India





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