IEEE Distinguished Lecture — Acceleration of Encryption Algorithms, Elliptic Curve, Pairing, Post Quantum Cryptoalgorithm (PQC)

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Abstract

 

This lecture will cover basics of public-key encryption, and example design optimization of elliptic-curve based encryption algorithm, including pairing operations, and its security measures. Then extend design optimization on lattice-based encryption algorithms including post quantum crypto-algorithm, CRISTALS-Kyber (FIPS 203 MLB-KEM)/Dilithium (FIPS204 MLB-DSS), hash based (FIPS 205 SHB-DSS), isogeny based encryption algorithms.

 


  Date and Time

  Location

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  Registration


  • Date: 14 Oct 2024
  • Time: 07:30 PM to 08:30 PM
  • All times are (UTC+08:00) Kuala Lumpur
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  • 1 Jalan Sultan Azlan Shah
  • Bayan Lepas, Pulau Pinang
  • Malaysia 11900
  • Building: PSDC
  • Room Number: 1201
  • Click here for Map
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  • Co-sponsored by Technological Association Malaysia

  Speakers

Prof. Dr. Makoto Ikeda of University of Tokyo

Topic:

Acceleration of Encryption Algorithms, Elliptic Curve, Pairing, Post Quantum Cryptoalgorithm (PQC)

Abstract

 

This lecture will cover basics of public-key encryption, and example design optimization of elliptic-curve based encryption algorithm, including pairing operations, and its security measures. Then extend design optimization on lattice-based encryption algorithms including post quantum crypto-algorithm, CRISTALS-Kyber (FIPS 203 MLB-KEM)/Dilithium (FIPS204 MLB-DSS), hash based (FIPS 205 SHB-DSS), isogeny based encryption algorithms.

Biography:

Speaker

Prof. Dr. Makoto Ikeda

Makoto Ikeda received the BE, ME, and Ph.D. degrees in electrical engineering from the University of Tokyo, Tokyo, Japan, in 1991, 1993 and 1996, respectively. He joined the University of Tokyo as a research associate, in 1996, and now professor and director of Systems Design Lab (d.lab), the University of Tokyo.

At the same time, he has been involving the activities of VDEC (VLSI Design and Education Center, the University of Tokyo), to promote VLSI design educations and researches in Japanese academia.  He worked for hardware security, asynchronous circuits design, smart image sensor for 3-D range finding, and time-domain signal processing. He has been serving various positions of various international conferences, including ISSCC ITPC Chair (ISSCC 2021), IMMD sub-committee chair (ISSCC 2015-2018), A-SSCC 2015 TPC Chair, VLSI Circuits Symposium PC Chair (2017) & Symposium Chair (2019).  He is a senior member of IEEE, IEICE Japan, and a member of IPSJ and ACM.

 

Email:

Address:Tokyo, Japan