IEEE BV COMSOC Talk: PRBS Patterns – Theory, Generation, Checking, Uses, Pitfalls, and Practical Implementation
PRBS patterns are ubiquitous in today's highly connected digital world. The acronym PRBS stands for "Pseudo-Random Binary Sequence", and as the name implies, they exhibit many characteristics of random data, yet with completely predictable deterministic behavior. These properties are of great theoretical importance, but what really makes them really valuable is the ease at which they can be implemented in both hardware and software from the smallest ultra-high performance 100GHz RF flip-flops, to the largest enterprise software applications.
This talk starts with the basic concepts of how they work, and how they can be visualized and understood in a simple way and follows up by numerous practical examples of generating and checking PRBS sequences in SPICE, Verilog, and Python. A practical example of testing an 8B/10B encoded communication channel will also be discussed. All examples will be shared for hand-on experimentation, as the greatest understanding usually comes when you can try something out yourself!
Date and Time
Location
Hosts
Registration
- Date: 12 Nov 2024
- Time: 06:30 PM to 08:00 PM
- All times are (UTC-08:00) Pacific Time (US & Canada)
-
Add Event to Calendar
- 31416 Agoura Rd
- Westlake Village, California
- United States 91361
- Building: Cal Lutheran Center for Entrepreneurship (Hub101)
- Starts 31 October 2024 12:00 AM
- Ends 12 November 2024 06:30 PM
- All times are (UTC-08:00) Pacific Time (US & Canada)
- No Admission Charge
Speakers
Mr. Greg Warwar
PRBS Patterns – Theory, Generation, Checking, Uses, Pitfalls, and Practical Implementation
Biography:
Greg Warwar is a native of Ventura County. He received a master’s degree in electrical engineering from Rice University in 1989. Following graduation, he joined Texas Instruments in Dallas, TX as a member of the technical staff where he worked on analog to digital converters for precision audio applications. In 1992, he joined Vitesse Semiconductor in Camarillo, CA where he worked for 23 years on high-speed serial communications ICs, focusing on many areas of analog and mixed-signal design including VCOs, phase-locked loops, clock recovery, frequency synthesizers, and adaptive equalization. Since 2015, Greg has worked as an analog / mixed-signal ASIC designer at Continental, HRL, and Teradyne in Agoura Hills, CA. Greg holds seven U.S. patents in the area CMOS mixed-signal IC design.
Email:
Agenda
- 6:30 - 7:00 Networking
- 7:00 - 8:00 Technical Talk