Dr. Rajiv Joshi of IBM, T. J. Watson Research Center

As semiconductor technology enters the sub-5nm era, geometry, process, voltage, and temperature (PVT) variability in devices can affect the performance, functionality, and power of circuits, especially in new Artificial Intelligent (AI) accelerators. This is where predictive failure analytics is extremely critical. It can identify the failure issues related to logic and memory circuits and drive the circuits in the energy-efficient area. This talk describes how key statistical techniques and new algorithms can be effectively used to analyze and build robust circuits. These algorithms can be used to analyze decoders, latches, and volatile as well as non-volatile memories. In addition, how these methodologies can be extended to “reliability prediction” with “hardware corroboration”. Also, logistic regression-based machine learning (ML) techniques are employed for modeling the circuit response and speeding up the Important Sampling techniques. To avoid overfitting, a cross-validation-based regularization framework for ordered feature selection is demonstrated. Also, techniques to generate accurate parasitic capacitance modeling along with PVT variations for sub-22nm technologies and their incorporation into a physics-based statistical analysis methodology for accurate Vmin analysis are described. Using such innovative techniques device mismatches in memory and their impact on circuit performance in Technology CAD (TCAD) are highlighted. Finally, the talk summarizes important issues in this field.

Biography:

Dr. Rajiv V. Joshi is an IEEE Fellow, winner of the prestigious IEEE Daniel Noble award, and a key technical lead/Research Scientist at T. J. Watson research center, IBM. He received his B.Tech IIT (Bombay, India), M.S (MIT), and Dr. Eng. Sc. (Columbia University). He has led successfully predictive failure analytic techniques for yield prediction and also the technology-driven SRAM at IBM Server Group. His statistical techniques are tailored for machine learning and AI which are licensed and commercialized. He received 3 Outstanding Technical Achievement (OTAs), 3 highest Corporate Patent Portfolio awards for contributions in interconnect technologies, holds 68 invention plateaus, and has over 278 US patents covering front end and back end of the line processes and structures, volatile and non-volatile memories, Compute in Memory structures, machine learning algorithms and quantum computing and over 415 international patents. He has authored and co-authored over 220 papers and given over 60 invited/keynote talks and given several Seminars. He received the NY IP Law association “Inventor of the year” award in Feb 2020. He received an industrial pioneer award in 2014 from IEEE Circuits and Systems society. He received the Best Editor Award from the IEEE TVLSI journal. He is inducted into the New Jersey Inventor Hall of Fame in Aug 2014. He won the Mehboob Khan award two times from Semiconductor Research Corporation. He won several best paper awards from ISSCC 1992, ICCAD 2012, ISQED, and VMIC. He is a member of the IBM Academy of technology and a master inventor. He serves on the Board of Governors for IEEE CAS as an industrial liaison. He serves as an IEEE CAS Ambassador to India. He served as a Distinguished Lecturer for IEEE CAS, CEDA, and EDS society. He is an ISQED and World Technology Network fellow and distinguished alumnus of IIT Bombay.

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