Renold Sam

Abstract:
This presentation focuses on the importance of testing in the semiconductor industry, specifically the role of Design for Testability (DFT) in ensuring that integrated circuits (ICs) can be tested efficiently and effectively. We will explore how DFT helps identify manufacturing defects and ensures proper functionality across various technologies. The presentation will cover defect and fault modeling, with an in-depth discussion on stuck-at and transition faults using scan chain architecture. Additionally, we will delve into Boundary-Scan Description Language (BSDL) for JTAG and Built-In Self-Test (BIST) for memory testing. The session will conclude with an overview of the DFT handshake with Automated Test Equipment (ATE) testers.

Biography:

Speaker biography:
Dr. Renold serves as the Senior Manager of DFT at Microchip. He oversees a team of over 70 engineers across four geographical locations and is currently managing eight projects. His areas of specialization include BSDL, achieving 99.5% test coverage, CAT, silicon bring-up, and post-silicon debug. He has successfully completed over 15 tape-outs, facilitated the bring-up of 3D ICs, and is working on 3nm designs. Additionally, he is currently focused on advanced fault modeling techniques. Prior to his tenure at Microchip Technology Inc., Dr. Renold held the position of Senior Manager of DFT at AMD Technologies and served as Associate Director of DFT at Samsung Technologies, where he worked on 3D ICs for AI chips.

Dr. Renold has completed his PhD in DFT techniques for FinFET circuits. He has published papers on Cell-Aware Testing, Test Point Insertions to increase test coverage, and 3D IC testing methodologies. Additionally, he serves as an Adjunct Professor at various universities, where he mentors master’s program students and research scholars. His research interests include exploring advanced fault modeling techniques in DFT.

Address:Canada