Dr. Ujjwal Guin of Auburn University, USA

Reducing manufacturing defect escape in safety-critical applications demands higher fault coverage, yet achieving 100% fault coverage still remains a challenge. Concurrently, the hardware security community addresses logic locking to combat IP piracy by embedding locks in netlists, requiring correct key input for proper functionality. However, SAT-based attacks, introduced by Subramanyan et al., efficiently recover secret keys no matter where they are placed and compromise logic-locking schemes. This talk focuses on (1) analyzing SAT attack complexity and (2) a novel SAT attack-driven test pattern generation method for logic circuits, treating stuck-at faults as locked gates with secret keys. This approach minimizes backtracking during SAT attack, deriving input patterns that determine the key and serve as tests for stuck-at faults

Biography:

Ujjwal Guin is currently an Associate Professor at the Department of Electrical and Computer Engineering at Auburn University. He received Bryghte D. and Patricia M. Godbold Associate Professorship for the highest research, teaching, and service achievements at Auburn University. He received his Ph.D. degree from the University of Connecticut in 2016. He is actively involved in projects in the fields of Hardware Security and Trust, Supply Chain Security, Cybersecurity, and VLSI Design and Test. He has developed several on-chip structures and techniques to improve the security, trustworthiness, and reliability of integrated circuits. He co-authored the book "Counterfeit Integrated Circuits: Detection and Avoidance''. He also authored two book chapters, over thirty journal articles, and forty refereed conference papers. His work has been recognized through several best paper nominations, awards, research grants, and prizes from various security competitions. One of his papers has been referenced in the "White House 100-Day Reviews under EO 14017" report, specifically in the context of "Building Resilient Supply Chains," dated June 2021. His projects are sponsored by the United States Army, Air Force Office of Scientific Research (AFOSR), Secret Service, National Science Foundation (NSF), and Air Force Research Laboratory (AFRL). He currently serves or has served several technical program committees in several reputed conferences, such as DAC, HOST, VTS, PAINE, VLSID, GLSVLSI, ISVLSI, and Blockchain. He is the Program Co-Chair of HOST 2025 and ATS 2024. He is a senior member of IEEE and a member of ACM.

Address:United States