Prof. Francesca Iacopi of IMEC, USA

Abstract: Advances in the epitaxial graphene growth on silicon carbide wafers have led to exciting developments, including the achievement of ballistic conduction and semiconducting properties on the same platform, which may greatly benefit future SiC technologies [1, 2]. In parallel, the harnessing of graphene’s properties on silicon wafers, despite inherent challenges, could deliver a broad range of miniaturized and fast reconfigurable functionalities to complement CMOS technologies in a system with the smallest form-factor. Over the last decade, we have pioneered an epitaxial graphene on silicon carbide on silicon technology able to fill this gap and, in addition, able to unlock unique functionalities for MEMS/NEMS, nano-optics and metasurfaces thanks to the specific combination of graphene with silicon carbide [3, 4, 5]. This platform allows to fabricate any complex graphene flat or 3D nanopattern in a site – selective fashion, ie without etching the graphene, at the wafer -scale and with sufficient adhesion for subsequent integration [3, 6]. We will review the fundamental hallmarks of this technology and some of its most promising applications. First, we show that the sheet resistance of epitaxial graphene on 3C-SiC on silicon is comparable to that of epitaxial graphene on SiC wafers, despite substantially smaller grains. We indicate that the control of the graphene interfaces, particularly when integrated, can be a more important factor than achieving large grain sizes [6]. Also, we show that well- engineered defects in graphene are preferable to defect -free graphene for most electrochemical applications. We will share exciting examples of application of this technology in areas as diverse as integrated energy storage [7], reconfigurable metasurfaces for MIR sensing and detection [8], and electrodes for electro-encephalography [9, 10] for brain-computer interfaces [11]. [1] J.Zhao et al., Nature 625, 60–65, 2024 [2] F.Iacopi, A.C.Ferrari, Nature 625, 34-35, 2024 [3] B.Cunning et al, Nanotechnology 25 (32), 325301, 2014 [4] E.Romero et al., Physical Review Applied 13 (4), 044007, 2020 [5] P.Rufangura e al, Journal of Physics: Materials 3 (3), 032005, 2020 [6] D.Katzmarek et al, Nanotechnology 34 (40), 405302, 2023 [6] A.Pradeepkumar et al, ACS Applied Nano Materials 3 (1), 830-841, 2019 [7] M.Amjadipour, D.Su and F.Iacopi, Batteries & Supercaps 3 (7), 587-595, 2020 [8] P.Rufangura et al, Nanomaterials 11 (9), 2339, 2021 [9] S.Faisal et al, Journal of Neural Engineering 18 (6), 066035, 2021 [10] S.Faisal et al, ACS Appl. Nano Mater. 6 (7), 5440-5447, 2023 [11] F.Iacopi and CT Lin, Progress in Biomedical Eng. 4 (4), 043002, 2022.

Biography:

Professor Francesca Iacopi is an IEEE Fellow with over 20 years’ industrial and academic research expertise in semiconductor technologies spanning interconnects, CMOS devices and packaging. Her research focuses on the translation of basic scientific advances in nanomaterials and novel device concepts into implementable integrated technologies. She is known for her seminal work on the integration of porous dielectrics in on-chip interconnects, and for the invention of the alloy -mediated epitaxial graphene platform on SiC on silicon wafers. She was recipient of an MRS Gold Graduate Student Award (2003), an Australian Research Council Future Fellowship (2012), a Global Innovation Award in Washington DC (2014) and was listed among the most innovative engineers by Engineers Australia (2018). Francesca is an IEEE EDS Distinguished Lecturer and serves regularly in technical and strategic committees for IEEE and the Materials Research Society. She is an Elected Member to the IEEE EDS Board of Governors (2021, 2024) and serves in the Editorial Advisory Board for ACS Applied Nanomaterials, and the IEEE The Institute magazine. She is also the inaugural Editor-in-Chief of the IEEE Trans. on Materials for Electron Devices (IEEE T-MAT). In 2024, she has left her tenured professorship in the Faculty of Engineering and IT, University of Technology Sydney, to join Imec USA in the role of Director of the Imec R&D site based at Purdue University, IN, USA.

Email:

Address:Director of Semiconductor R&D, IMEC USA, , IN, Indiana, United States, 47901