FPGA based Hardware Acceleration
IEEE Computer Society Chapter, Vizag Bay Section
This is to inform you all that Computer Society Chapter of IEEE Vizag Bay Section is organizing an invited talk on FPGA based Hardware Acceleration on 27th September, 2024 from 6.30 PM onwards.
Speaker: Kavinga Upul Ekanayaka, Head of Hardware Acceleration at ACCELR, Colombo. Sri Lanka.
UG/PG Students, Research Scholars, Academicians and Participants from Industry may attend.
Date: 27-09-2024, 06.30 PM onwards.
Registration is Free but mandatory. WebEx Link will be shared to all through registered mail Id. Also requested to join WhatsApp link given in registration form.
Registration Link: https://forms.gle/7erW1YvC4SQP4CUK7
All the SB Counsellors / HODs / Faculty Members are requested to share and encourage more participation from your institute.
With regards,
Computer Society Team, Vizag Bay Section
Date and Time
Location
Hosts
Registration
-
Add Event to Calendar
Loading virtual attendance info...
- Contact Event Host
- Co-sponsored by IEEE Vizag Bay Section
Speakers
Kavinga Upul Ekanayaka of ACCELR, Colombo
FPGA based Hardware Acceleration
This is to inform you all that Computer Society Chapter of IEEE Vizag Bay Section is organizing an invited talk on FPGA based Hardware Acceleration on 27th September, 2024 from 6.30 PM onwards.
Speaker: Kavinga Upul Ekanayaka, Head of Hardware Acceleration at ACCELR, Colombo. Sri Lanka.
He speak about Hardware acceleration in chip design and GPU design
Biography:
About
Email:
Address:16, Station Road Colombo 4, Colombo, Sri Lanka, Sri Lanka, 00400
Agenda
Welcome Note by Dr. P. Sivakumar
Speaker Introduction by Anji Reddy
Speaker: Kavinga Upul Ekanayaka, Head of Hardware Acceleration at ACCELR, Colombo. Sri Lanka.
Vote of Thanks by Dr. V Chandra Sekhar, Vice Chair
IEEE Vizag Bay Section
Media
| Flier | 250.89 KiB |