IEEE SSCS/CAS Webinar: New Directions in Power Management - consolidation and computation by Prof. Visvesh Sathe, Georgia Tech

#sscs #cas #powermanagement #hpc #thermal #soc
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  • Date: 27 Feb 2025
  • Time: 12:00 PM to 01:00 PM
  • All times are (UTC-06:00) Central Time (US & Canada)
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  • Starts 08 February 2025 01:19 PM
  • Ends 27 February 2025 12:00 PM
  • All times are (UTC-06:00) Central Time (US & Canada)
  • No Admission Charge


  Speakers

Vish of Georgia Institute of Technology

Topic:

New Directions in Power Management: consolidation and computation

Power management remains a critical enabler in the design of energy-efficient SoCs, with Voltage Regulator (VR) design representing a cornerstone of the effort. Converter efficiency was traditionally the governing metric in VR design – and rightly so. However, the relentless pursuit of enhanced SoC efficiency is driving evolution of power management toward the design of power delivery systems focused on enhancing overall system efficiency for designs with large domain counts across a broad range of PVT parameters. Meanwhile, 3D Heterogeneous Integration trends are expected to intensify the importance of modeling Power Distribution Networks and run-time thermal management.

In this talk, I will introduce my group, the Processing Systems Lab (PSyLab) and the work they have been doing in exploring new directions in power management. The first half of the talk will provide an overview of several projects whose applications range from ultra low-power duty cycled systems to high-performance processors. I will discuss two recent projects that represent these new directions in particular: (1) DRIVR, a Digitally Reconfigurable IVR Fabric, and (2) Thermal Sensor Design for SoCs. I will discuss test chip measurements for some of these approaches that reveal both, their latent promise and some of the associated challenges in translating them into volume production.

Biography:

Vish is an Associate Professor at the Georgia Institute of Technology, where his group, the Processing Systems lab, works on digital, mixed-signal, and integrated power circuit architectures for energy-efficient processing. He has previously held positions at UW and at the Low-power Advanced Development Group at AMD, where he developed or co-developed a number of key technologies for energy-efficient processors, such as resonant clocking and adaptive clock stretching, into volume production. He was a distinguished lecturer of the IEEE Solid-State Circuits Society in 2020-2021. He currently chairs the IEEE SSCS webinar committee to promote professional and student development and is a member of the Technical Program Committee of the CICC and ISSCC.