SIGNAL PROCESSING ALGORITHMS INTO FIXED-POINT FPGA HARDWARE

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Digital signal, image and data processing executing sequentially on a conventional device can be enhanced by the unique vector and parallel processing capabilities of the field programmable gate array (FPGA). Conventional processors are generally scalar and sequential, albeit with pipeline architectures, floating point operations and higher speed logic but with more power consumption than an FPGA. The FPGA can execute in parallel as a vector operation but optimally with fixed point operations which require a quantization analysis of the processing algorithm to be implemented. The MathWorks Fixed Point Designer™ facilitates this analysis and the FPGA can use registers of any size throughout the various stages of the processing algorithm.

The Fixed-Point Designer provides data types and tools for developing fixed-point algorithms and automatically proposes fixed-point data types and attributes such as word length, the fixed point rounding mode and the action to be taken on register overflow. Bit-true simulations are then used to observe the impact of the limited range and precision. The Fixed-Point Designer can also convert floating-point algorithms to fixed point by specifying fixed-point data types that meet the numerical accuracy requirements and hardware constraints.



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  • Temple University
  • 1947 N. 12th St.
  • Philadelphia, Pennsylvania
  • United States 19122
  • Building: Engineering Building
  • Room Number: Room E301, 3rd Floor
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  • Co-sponsored by System Chip Design Lab, Temple University and IEEE Computer Society
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  Speakers

Dr. Dennis Silage of Temple University

Topic:

SIGNAL PROCESSING ALGORITHMS INTO FIXED-POINT FPGA HARDWARE

Digital signal, image and data processing executing sequentially on a conventional device can be enhanced by the unique vector and parallel processing capabilities of the field programmable gate array (FPGA). Conventional processors are generally scalar and sequential, albeit with pipeline architectures, floating point operations and higher speed logic but with more power consumption than an FPGA. The FPGA can execute in parallel as a vector operation but optimally with fixed point operations which require a quantization analysis of the processing algorithm to be implemented. The MathWorks Fixed Point Designer™ facilitates this analysis and the FPGA can use registers of any size throughout the various stages of the processing algorithm.


The Fixed-Point Designer provides data types and tools for developing fixed-point algorithms and automatically proposes fixed-point data types and attributes such as word length, the fixed point rounding mode and the action to be taken on register overflow. Bit-true simulations are then used to observe the impact of the limited range and precision. The Fixed-Point Designer can also convert floating-point algorithms to fixed point by specifying fixed-point data types that meet the numerical accuracy requirements and hardware constraints.

Biography:

Dr. Dennis Silage received the PhD in Electrical Engineering and Biomedical Engineering from the University of Pennsylvania in 1975. Prior to joining the Faculty at Temple University in 1984, he had a biomedical research career, with research faculty and adjunct faculty appointments at the University of Pennsylvania, School of Medicine, the Medical College of Pennsylvania and the Mount Sinai Medical School. Dr. Silage has been a Professor of Electrical and Computer Engineering at Temple University since 1984, teaches digital data communication, digital signal and image processing and embedded processing systems. His research is in these areas with high performance, real-time computational architectures using field programmable gate arrays. He has recently supervised four PhD candidates to completion and twenty-two MSE students. Dr. Silage is past chair of the Electrical and Computer Engineering Division of the American Society for Engineering Education (ASEE), recipient of the 2007 ASEE National Outstanding Teaching Award, the 2011 ASEE ECE Division Meritorious Service Award, the Lindbach Distinguished Teaching Award in 2012. He is a Life Senior Member of the Institute of Electrical and Electronics.

Email:

Address:1947 N. 12th St., , Philadelphia, Pennsylvania, United States, 19122

Dr. Dennis Silage of Temple University

Topic:

SIGNAL PROCESSING ALGORITHMS INTO FIXED-POINT FPGA HARDWARE

Biography:

Email:

Address:Philadelphia, Pennsylvania, United States