Wladek

 Abstract: The semiconductor industry has been evolving and innovating for the past 75 years, ever since the first semiconductor transistor was invented. This rapid growth is driven by the direct and proactive contribution of the FOSS CAD/EDA to the entire technology flow: from state-of-the-art semiconductor technologies, device level compact/SPICE modeling, its Verilog-A standardization to advanced IC designs for various HiTech applications. However, the semiconductor industry also faces many challenges in maintaining the growth of its workforce with skilled technicians and engineers. To address the increasing need for well-trained workers worldwide, we need to find innovative ways to attract skilled talent and strengthen the local semiconductor workforce ecosystem. The FOSS CAD/EDA tools with the recently available OpenPDKs provide a new platform to connect IC design beginners, enthusiasts and experienced mentors to benefit from the collaboration opportunities enabled by the fast-growing open-source IC design movement. FOSS IC design collaboration is increasingly possible due to the rapid growth of OpenPDKs recently offered by SkyWater, GF and IHP. This paper demonstrates the FOSS CAD/EDA contribution to the SPICE/Verilog-A modeling/standardization, compete IC design flow (Xschem, Qucs-S, ngspice, Xyce, OpenVAF, OpenEMS, Magic, kLayout, OpenRoad) as well as selected open source analog/RF and digital IC design examples. 

Biography:

 Wladek Grabinski received the Ph.D. degree from the Institute of Electron Technology, Warsaw, Poland, in 1991. From 1991 to 1998 he was a Research Assistant at the Integrated Systems Lab, ETH Zürich, Switzerland, supporting the CMOS and BiCMOS technology developments by electrical characterization of the processes and devices. From 1999 to 2000, he was with LEG, EPF Lausanne, and was engaged in the compact MOSFET model developments supporting numerical device simulation and parameter extraction. Later, he was a technical staff engineer at Motorola/FSL, Geneva Modeling Center, Switzerland. He is now a consultant responsible for modeling, characterization and parameter extraction of MOS transistors for the design of RF CMOS circuits in OpenPDK. His current research interests are in high-frequency characterization, compact modeling and its Verilog-A standardization as well as device numerical simulations of MOSFETs for analog/RF low power IC applications. He is currently consulting on the development of next-generation compact models for the VLSI integration and OpenPDK IC simulation. He is an author of the reference “Compact/SPICE Modeling” chapter in the Springer Handbook of Semiconductor Devices, and also authored or coauthored more than 70 papers. Wladek has established ESSDERC TPC Track3: "Device and Circuit Compact Modeling" as well as was serving as a member of the IEEE EDS Compact Modeling Technical Committee, European representative in the ITRS Modeling and Simulation Working Group; organization committees of ESSERC, TPC of SBMicro, SISPAD, MIXDES Conferences; reviewer of the IEEE TED, IEEE MWCL, IJNM, MEE, MEJ. He was a Member At Large of Swiss IEEE ExCom and mentor of the EPFL IEEE Student Branch, now. Wladek is involved in activities of the MOS-AK Association and serves as a coordinating R&D manager since 1999.