Oregon CAS/EPS & SMTA Oregon - 3D SiP for ASIC and Memory Integration
IEEE Oregon Joint CPMT/CAS Chapter
(in cooperation with SMTA, IMAPS, IPC & EMA)
Topic: 3D SiP for ASIC and Memory Integration
Speaker: Dr. Li Li, Cisco Systems, Inc.
Date: Thursday, November 16th, 2017, 6.00–8.00pm
Location: PCC Willow Creek Center, Room 313
241 SW Edgeway Drive (near SW 185th and Baseline Road) Beaverton, OR 97006
(seminar room sponsored by the PSU ECE department)
Date and Time
- Date: 16 November 2017
- Time: 06:00 PM to 08:00 PM
- All times are US/Pacific
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- 241 SW Edgeway Drive
- Beaverton, Oregon
- United States 97006
- Building: PCC Willow Creek Center
- Room Number: 313
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- Co-sponsored by SMTA, IMAPS & EMA
- Registration closed
Dr. Li Li of Cisco Systems
3D SiP for ASIC and Memory Integration
To meet the requirements of next generation Information and Communication Technology (ICT) systems, the packaging technology has to evolve along with the silicon technology node scaling as predicted by Moore’s Law. At the same time, design and development of packages have to meet the cost, performance, form factor and reliability goals. In this talk, we will examine the role of emerging 2.5-Dimensional (2.5D) and 3-Dimensional (3D) IC packaging platforms for addressing the gap seen between the slowdown of Moore’s Law scaling and the ever-increasing system integration requirements. System integration based on the 3D System-in-Package (3D SiP) technology has been developed for integrating Application Specific Integrated Circuits (ASICs) and memory devices. We will review the new elements introduced by 2.5D and 3D IC packaging and the potential risks to reliability of the final products. A detailed review on technology and component level qualification will be presented. It will then be followed by two examples as case studies on board level reliability validation.
Dr. Li LI is a Distinguished Engineer at Cisco Systems, Inc. where he leads an initiative on 3D IC integration and advanced packaging development. He has been with Cisco since 2004 and has over 20 years industry experience in IC packaging design, technology development and qualification.
Dr. Li has published several book chapters and over 50 technical papers in the field of microelectronics packaging. He is on the Board of Governors of IEEE Electronics Packaging Society (formerly CPMT) and the Board of Directors of HDP User Group International (HDPUG), Inc.
He received his M.S. and Ph.D. degrees in Mechanical Science and Engineering from the University of Illinois at Urbana-Champaign.
Address:Cisco Systems, Inc., , California, United States
6:00pm Refreshments and social
7:30pm Questions and Discussion