SSCS UK and Ireland DL : Prof Shanthi Pavan : Precision CT Delta Sigma

#SSCS #ADC #delta-sigma #data-conversion #converters #circuits
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Design Challenges in Precision Continuous-Time Delta Sigma Data Conversion

Energy-efficient, high-resolution continuous-time delta-sigma modulators need to overcome several issues that are typically neglected in the design of data converters that target more modest in-band noise spectral densities. Examples of such problems include flicker noise, interconnect resistance and DAC inter-symbol-interference. This talk aims to provide some insight into these issues and describe techniques that can be used to address the formidable challenge of designing such converters. To place things in perspective, the techniques will be discussed in the context of single- and multi-bit CTDSMs that achieve about 105dB SNDR in a 250kHz bandwidth designed in a 180nm CMOS process.



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  • Date: 21 May 2025
  • Time: 11:00 AM UTC to 12:25 PM UTC
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  • Tyndall National Institute
  • Lee Maltings, Dyke Parade,
  • Cork, Cork
  • Ireland T12 R5CP
  • Room Number: B.0.17
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  • Starts 13 May 2025 11:00 PM UTC
  • Ends 20 May 2025 11:00 PM UTC
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  Speakers

Shanthi Pavan

Topic:

Prof Shanthi Pavan

Biography:

Shanthi Pavan received the B.Tech. degree in electronics and communication engineering from IIT Madras, Chennai, India, in 1995, and the M.S. and D.Sc. degrees from Columbia University, New York, NY, USA, in 1997 and 1999, respectively. From 1997 to 2000, he was with Texas Instruments, Warren, NJ, USA, where he worked on high-speed analog filters and data converters. From 2000 to June 2002, he worked on microwave ICs for data communication at Bigbear Networks, Sunnyvale, CA, USA. Since July 2002, he has been with IIT Madras, where he is currently the NT Alexander Institute Chair Professor of Electrical Engineering.Prof.Pavan is the author of Understanding Delta-Sigma Data Converters (second edition, with Richard Schreier and Gabor Temes), which received the Wiley-IEEE Press Professional Book Award for the year 2020. His research interests are in the areas of high-speed analog circuit design and signal processing. Dr. Pavan is a fellow of the Indian National Academy of Engineering, and the Indian National Science Academy, and the recipient of several awards, including the IEEE Circuits and Systems Society Darlington Best Paper Award in 2009. He has served as the Editor-in-Chief of the IEEE Transactions on Circuits and Systems—I: Regular Papers and on the Technical Program Committee of the International Solid-State Circuits Conference (ISSCC). He has served as a Distinguished Lecturer of the IEEE Circuits and Systems Society and is a two-term Distinguished Lecturer of the Solid-State Circuits Society. He currently serves as the Vice-President of Publications of the IEEE Solid-State Circuits Society and on the editorial board of the IEEE Journal of Solid-State Circuits. He is an IEEE Fellow.