3D Power Management and Delivery for High-Performance Computing and AI Chips
In today’s rapidly advancing landscape of artificial intelligence (AI), big data, edge computing, and cloud computing, high-performance computing (HPC) systems are essential to modern life. The AI datacenter market, projected to exceed $1 trillion annually by 2029, underscores the critical role of HPC/AI chips. However, as these systems grow more versatile and power-intensive, chip-level power delivery in the last “inch” has emerged as a significant bottleneck, where even small gains in power efficiency are crucial. This challenge has driven innovations in 3D/2.5D packaging and vertical power delivery, which offer advantages such as reduced energy loss and mitigated IR drop, exemplified by Intel, TSMC, and Samsung’s backside power solutions and Tesla’s Dojo. To address current stress at the board and bump levels, integrated voltage regulators (IVRs) compatible with 3D backside power delivery have been introduced, including (a) µm-thin-profile capacitive IVRs with high-density 2.5D MIM capacitors and (b) high-power-density inductive IVRs with high-Q 3D inductors. This presentation focuses on the critical building blocks of 3D backside power delivery, covering device processing, heterogeneous package integration, and system-level design. Furthermore, materials, passive components, and circuits are considered as a whole, with the Design-Technology Co-Optimization (DTCO) approach proposed as a key enabler for boosting power conversion efficiency. Lastly, we will outline future directions for 3D power delivery in HPC/AI systems, including advancements in devices, the DTCO approach, and chiplet level.
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