Functional Verification of RTL Digital Designs: Crux & Craft

#VLSI #Design #RTL #Digital #Functional #Verification #SV-UVM #challenges #and #complexity #of #the #verification #problem
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The IEEE LI Chapter Signal Processing Society (SPS) presents the following Technical Lecture:

Abstract:

This webinar provides insights on the need for verification methodologies like SV-UVM & Formal for RTL Design verification in the VLSI Design Cycle. We will discuss the challenges and complexity of the verification problem while discussing various verification tools available in the industry to solve them.



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  • Starts 01 June 2025 04:00 AM UTC
  • Ends 25 September 2025 10:30 PM UTC
  • No Admission Charge


  Speakers

Dr. Anantharaj Thalaimalai Vanaraj of Samsung Austin Research Centre – Advanced Computing Lab (SARC-ACL)

Biography:

Dr. Anantharaj Thalaimalai Vanaraj did his bachelor’s degree in Electronics and Communication Engineering from Thanthai Periyar Govt. Institute of Technology (affiliated with Madras University, Tamil Nadu, India), master’s degree in VLSI Systems and doctorate in post-CMOS QCA technology from National Institute of Technology, Tiruchirappalli, Tamil Nadu, India. He has over 22 years of industry experience in semiconductor-based flash memory and digital design verification for consumer electronics, wireless, and storage 
applications. He works as a Formal Verification Leader with Samsung Austin Research Centre – Advanced Computing Lab (SARC-ACL), San Jose, California, USA. He is part of the hardware design and development group for Graphics Processing Unit (GPU) at the silicon level.   

He has delivered technical sessions at several international/national conferences, seminars, and workshops. He is also a senior grade member associated with the Santa Clara Valley chapter and the Solid-State Circuits Society (SSCS) of the IEEE association. He is an active volunteer of the IEEE SSCS Arduino Contest to motivate STEM education across the world. He is a renowned fellow of the Institute of Electronics & Telecommunication Engineering (IETE) - India, Institute of Engineering & Technology (IET) & British Computing Society (BCS) organizations in the U.K. He has extensive research and development experience in NAND Flash Memory design verification using IEEE 1800-based System Verilog and UVM. He had received seven US patents related to NAND Flash Memory and SSD products. He has published more than 20+ research articles, which are cited by more than 100 research articles. He is also a reviewer in various reputed international journals. His research area involves NAND Flash Memory, Memory Architecture, CMOS VLSI Digital Design, VLSI Logic/Functional Verification, and Quantum-dot Cellular Automata (QCA) designs.

Address:United States





Agenda:
7:00 pm -7:05 pm EDT - Introduction
7:05 pm -7:50 pm EDT - Technical Lecture
7:50 pm -8:00 pm EDT - Q&A and Wrap-up