DDR5 Memory Interface: Signal Integrity debugging and compliance testing

#DDR5 #LPDDR5 #SDRAM #DDR #memory #Interfaces #JEDEC #standards
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IEEE North Jersey Section Co-Sponsors the Talk: "DDR5 Memory Interface: Signal Integrity debugging and compliance testing"

 

 

 

Integrating DDR SDRAM memories into your design can be challenging. The increasing data rates with DDR5 and LPDDR5 demand even more care for signal integrity, the lower supply voltage decreases design margin, and the higher density of electronic components causes more potential interference sources.  This webinar will discuss discovering innovative test solutions for debugging error sources in your memory interface design and verifying margins and compliance with the DDR5 and LPDDR5 JEDEC specifications. 

You will learn:

  • Key challenges in integrating DDR5 and LPDDR5 SDRAM into your design
  • Advanced signal integrity debug tools specifically for DDR memory interfaces
  • Practical techniques like Zone Triggering to isolate READ/WRITE bursts
  • How to optimize your DDR5/LPDDR5 interface for peak performance and reliability
  • Running Automated Compliance Tests to ensure your design meets JEDEC standards

 

 

 

 


  Date and Time

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  • Ajay Poddar (akpoddar@ieee.org), Edip Niver (edip.niver@njit.edu), Durga Mishra (dmisra@njit.edu), (Anisha Apte (anisha_apte@ieee.org)

     

     

     

     

     

     

     

     

     

     

     

     

     

     

  • Co-sponsored by IEEE North Jersey Section

  Speakers

Guido Schulze of Rohde & Schwarz

Topic:

DDR5 Memory Interface – Signal integrity debugging and compliance testing

This webinar will discuss discovering innovative test solutions for debugging error sources in your memory interface design and verifying margins and compliance with the DDR5 and LPDDR5 JEDEC specifications. 

  • Key challenges in integrating DDR5 and LPDDR5 SDRAM into your design
  • Advanced signal integrity debug tools specifically for DDR memory interfaces
  • Practical techniques like Zone Triggering to isolate READ/WRITE bursts
  • How to optimize your DDR5/LPDDR5 interface for peak performance and reliability
  • Running Automated Compliance Tests to ensure your design meets JEDEC standards

 

 

 

 

Biography:

Guido Schulze has over 25 years of experience in high-speed digital testing. He started his career as an application engineer for Automated Test Equipment (ATE), focusing on emerging interfaces such as DDR, PCIe, and XAUI. For the past 15 years, he has served as a product manager in the oscilloscope division at Rohde & Schwarz in Munich, where he specializes in high-end oscilloscope models and their various applications.

Address:Rohde & Schwarz,

Johannes Ganzert of Rohde & Schwarz

Topic:

DDR5 Memory Interface – Signal integrity debugging and compliance testing

Integrating DDR SDRAM memories into your design can be challenging. The increasing data rates with DDR5 and LPDDR5 demand even more care for signal integrity, the lower supply voltage decreases design margin, and the higher density of electronic components causes more potential interference sources.  This webinar will discuss discovering innovative test solutions for debugging error sources in your memory interface design and verifying margins and compliance with the DDR5 and LPDDR5 JEDEC specifications. 

 

 

Biography:

 

Johannes Ganzert is a Senior Applications Engineer specializing in oscilloscopes at Rohde & Schwarz in Munich, Germany. After graduating from the Technical University of Munich, he began his career at Rohde & Schwarz as a Development Engineer focused on digital hardware and software. Over the years, Johannes has gained extensive experience in both RF and digital applications, with particular expertise in high-speed digital design and serial buses. He actively participates in several standardization consortia, including the OPEN Alliance and USB-IF.

Address:Munich, Germany