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Digital Design on FPGA Using Vivado
Digital Design on FPGA Using Vivado
The IEEE CAS (Circuits and Systems) Student Chapter organizing a technical session on
"Digital Design on FPGA Using Vivado" aimed at providing undergraduate students
with practical exposure to FPGA-based digital circuit design. The session focuses on the
complete FPGA design flow, the use of the Xilinx Vivado tool, and implementation of
combinational and sequential circuits using Verilog HDL. This initiative is part of the
chapter’s goal to promote awareness and technical proficiency in hardware design and
embedded systems.
Date and Time
Location
Hosts
Registration
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- Siddaganga Institute of Technology
- Tumakuru, Karnataka
- India 572103
- Building: Department of Electronics and Instrumentation
- Room Number: Seminar hall
Speakers
Anushree of SIT
FPGA Design Flow, Simulation and Testing of Verilog Design on FPGA(PYNQ Z2)
Explanation of the step-by-step design methodology including coding, simulation,
synthesis, implementation, and bitstream generation.
Email:
Address:SIT, , Tumakuru, Karnataka, India, 572103
Bhoomika of SIT
Basics of FPGA
Basics of FPGA
Email:
Address:SIT, , Tumakuru, Karnataka, India, 572103
Akshatha of SIT
Overview of Xilinx Vivado Design Suite
Overview of Xilinx Vivado Design Suite
Email:
Address:SIT, , Tumakuru, India, 572103
Charusmitha of SIT
Implementation of Combinational Circuits in Vivado
Implementation of Combinational Circuits in Vivado
Email:
Address:SIT, , Tumakuru, Karnataka, India, 572103
Shivadas of SIT
Implementation of Sequential Circuits in Vivado
Implementation of Sequential Circuits in Vivado
Email:
Address:SIT, , Tumakuru, Karnataka, India, 572013
Agenda
Practical exposure to FPGA-based digital circuit design
Department of Electronics and Instrumentation Engineering,
Siddaganga Institute of Technology,
Tumakuru