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FET100 and Golden Jubliee Celebration of IEEE Delhi Section: MOS Transistors: Myths and Errors in Understanding and Analysis
Dear All
You are all invited to register and attend the Technical Talks being organized by IEEE Electron Device Society (EDS) Delhi Chapter – India and IEEE EDS Community Engagement Ad-hoc Committee alongwith The National Academy of Sciences India-Delhi Chapter; Science Foundation Committee of Deen Dayal Upadhyaya College, University of Delhi, New Delhi, INDIA
Kindly register for each talk and encourage your students and other colleagues also.
July 14, 2025 @ 08:00 am your time (GMT - 7) i.e. 08:30 PM Indian Standard Time (GMT +5:30)
MOS Transistors: Myths and Errors in Understanding and Analysis
Colin McAndrew, IEEE Life Fellow
Threshold voltage V_T has a mythological status in MOS transistor analysis yet is a nebulous, imprecise quantity; V_T does not appear in the formulation of any modern, physically based MOS transistor model. What SPICE prints as the drain saturation voltage V_Dsat can be bizarrely wrong. The 2nd most important intrinsic MOS transistor capacitance in saturation, C_dg, is omitted in the small-signal models presented in all IC design textbooks, and is, despite what you have been taught, not Miller multiplied. “Standard” measures to compute MOS transistor drain current I_D mismatch in weak inversion are wrong and violate a fundamental physical requirement, that the variance of I_D pair mismatch must be twice the variance of the local variation in I_D of a single transistor. This talk will delve into those misconceptions about MOS transistors and will (hopefully) give you a better understanding of how MOS transistors work and how to analyze data from them.
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- Co-sponsored by Deen Dayal Upadhyaya College, University of Delhi, New Delhi 110078
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Colin
MOS Transistors: Myths and Errors in Understanding and Analysis
Threshold voltage V_T has a mythological status in MOS transistor analysis yet is a nebulous, imprecise quantity; V_T does not appear in the formulation of any modern, physically based MOS transistor model. What SPICE prints as the drain saturation voltage V_Dsat can be bizarrely wrong. The 2nd most important intrinsic MOS transistor capacitance in saturation, C_dg, is omitted in the small-signal models presented in all IC design textbooks, and is, despite what you have been taught, not Miller multiplied. “Standard” measures to compute MOS transistor drain current I_D mismatch in weak inversion are wrong and violate a fundamental physical requirement, that the variance of I_D pair mismatch must be twice the variance of the local variation in I_D of a single transistor. This talk will delve into those misconceptions about MOS transistors and will (hopefully) give you a better understanding of how MOS transistors work and how to analyze data from them.
Biography:
Colin McAndrew received the B.E. degree (Hons.) in electrical engineering from Monash University, Melbourne, VIC, Australia, and M.A.Sc. and Ph.D. degrees in systems design engineering from the University of Waterloo, Waterloo, ON, Canada. He worked at AT&T Bell Laboratories for 7 years, then for 29 years at NXP / Freescale / Motorola. He is now an Affiliate Full Professor at Iowa State University. He has over 150 publications (22 invited, 4 best paper), was an editor of IEEE TED for 9 years and IEEE JEDS for 9 years, has been on conference committees for IEEE BCTM, CICC, ICMTS, and BMAS, and received the SRC Mahboob Khan Outstanding Mentor Award. He drove the adoption of Verilog-A as the industry standard for SPICE modeling, chaired the IEEE EDS committee on compact modeling 2013-2016, and is a Life Fellow of the IEEE.