SystemVerilog for Verification

#device #sim #verilog #SSCS
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In semiconductor industry, a key factor for ensure the devices' quality and robustness is the verification process.

This course will be imparted to teach the methodology used in the verification of digital high speed circuits described in HDL languages.

This course comprises eight two-hour sessions, where examples will be created and tested using ModelSim-Intel software.


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  • Starts 01 July 2025 06:00 AM UTC
  • Ends 09 August 2025 06:00 AM UTC
  • No Admission Charge

  Speakers

Santiago of Micron Technology

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SystemVerilog for Verification

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Agenda

Tuesday 01/07/2025:       06:00PM to 08:00PM

Wednesday 02/07/2025:  06:00PM to 08:00PM

Thursday 03/07/2025:      06:00PM to 08:00PM

Friday 04/07/2025:           06:00PM to 08:00PM

Saturday 05/07/2025:      09:00AM to 11:00PM

Monday 07/07/2025:       06:00PM to 08:00PM

Tuesday 08/07/2025:       06:00PM to 08:00PM

Wednesday 09/07/2025:  06:00PM to 08:00PM


By the end of the course, an acknowledgement will be provided to each attendee who has taken completely the course.