Dr. Deepak Goyal, Fellow IEEE

Semiconductor Market growth is driven by (a) Computing and data storage, leading to
explosion of Data - sharing, storage and analytics (AI) and (b) Communication explosion – both
wireless and wired. The best response to this is Advanced Packaging or 3D Heterogeneous
Integration (HI). Packaging is the final manufacturing process transforming semiconductor
devices into functional products. Advanced packaging refers to a combination of distinct
technologies designed, processed, assembled & tested to enable cost, performance, power,
and size optimized interconnection of ICs and supporting elements to each other and to the
system, including flip chip on build-up substrates, wafer and panel level packaging, silicon
bridge, interposer with & w/o TSV (Through Silicon Vias); inclusive of the lateral (2D) and
vertical (3D) architectures [1].
The role of Advanced Packaging is to provide unprecedented levels of Heterogeneous
Integration (HI). HI refers to the integration of separately manufactured components into a
higher-level assembly that, in the aggregate, provides enhanced functionality and improved
operating characteristics [1]. This presentation will review the evolution of Advanced Packaging
for HI and also discuss the future scaling for HI. The Advanced Packaging technologies must
extend along multiple vectors to enable future HI Products. These vectors will be discussed and
will include Interconnect Scaling, Mainstreaming Optical Interconnects, High efficiency power
delivery networks, Thermal solutions for 2D and 3D, Manufacturing and Yield optimization.
Packaging Technology Evolution opens up multiple opportunities for roadmap development
and Research.

Biography:

Deepak Goyal graduated with a PhD from State University of New York, Stony Brook. He has
recently retired as Sr. Principal Engineer/Sr. Director, leading the Global Assembly and Test
(Technology Development and Manufacturing) Failure/Yield Analysis Labs at Intel. His
responsibilities included defect characterization, fault isolation, yield, failure and materials
analyses for the next generation package technology development at Intel; analytical chemistry
labs in support of the substrate development and manufacturing, and Board and System level

failure analysis; and development of the next generation of analytical metrologies, tools and
techniques. He has helped with the development of all Intel assembly technologies including
FCxGA, FCCSP, TSVs, POINT, EMIB, co-EMIB and Foveros. He is an expert in the defect
characterization, failure analysis and failure mechanism understanding for packages and has
taught Professional Development courses on Package FA/FI methods and failure mechanisms at
the Electronics Components and Technology Conference (ECTC). Deepak has authored and co-
authored over 60 papers and holds 19 US patents. He has co-authored 2 book chapters and has
co-edited 2 books on “3D Microelectronic Packaging”. He is an IEEE Fellow and an EPS
Distinguished Lecturer.