DSP Algorithm Development for FPGAs and HDL Code Generation

#digital-signal-processing #matlab #FPGA
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Join us for an engaging four-day course that delves into the fundamentals of Digital Signal Processing (DSP) from the perspective of implementation within the FPGA fabric.  Particular emphasis will be placed on highlighting the costs, in terms of both resources and performance, associated with implementing various DSP techniques and algorithms. The course will be delivered by world class experts from MathWorks. 
Topics include:

  • Introduction to FPGA hardware and technology for DSP applications
  • DSP fixed-point arithmetic
  • Signal flow graph techniques
  • Fast Fourier Transform (FFT) Implementation
  • Design and implementation of FIR, IIR and CIC filters
  • CORDIC algorithm
  • HDL code generation for FPGAs
  • Integrating handwritten code and existing IP
  • Verifying generated HDL code using testbench and co-simulation

 
PREREQUISITES

MATLAB® Fundamentals and Signal Processing with Simulink® or equivalent experience.


PRICE

Ticket Type Early Bird Standard
Student - IEEE Member $1700 $1800
Student - General $1900 $2000
IEEE Member $2300 $2500
General $2800 $3000

 

SPECIAL OFFERS

To take advantage of our early bird pricing, please register by 31 August 2025 to secure your spot at a discounted rate.

 

Group discounts are available. Contact the organisers for more details.


  Date and Time

  Location

  Hosts

  Registration


  • Add_To_Calendar_icon Add Event to Calendar
  • University of Adelaide
  • Adelaide, South Australia
  • Australia 5000
  • Building: Ingkarni Wardl
  • Room Number: B16
  • Click here for Map
  • Contact Event Host

  Speakers

Sivaselvi Periyasamy of MathWorks

Biography:

Dr Sivaselvi Periyasamy is a Senior Training Engineer at MathWorks India Private Limited and works in
training customers on MathWorks’ products for Signal Processing & Communication. Prior to joining
MathWorks, Sivaselvi worked as a Project Associate at Centre for Industrial Consultancy and
Sponsored Research at Indian Institute of Technology, Madras focusing on Acoustic mode variability.
Sivaselvi’s research interest includes Detection and Estimation theory, Wave Hydrodynamics, Ocean
Acoustics and Signal Processing.
She holds a Ph.D. degree in Ocean Engineering from Indian Institute of Technology, Madras. Her
research thesis focused on developing a broadband model for sound propagation in deep water
(MATLAB). She holds a master’s degree in VLSI Design and a bachelor’s degree in Electronics and
Communications Engineering, both from the Bannari Amman Institute of Technology, Tamil Nadu,
India.




Agenda

Day 1- DSP for FPGAs

  • FPGA Fundamental Concepts

  • Signal Flow Graph (SFG) Techniques (SFG) Technique

  • Digital Filtering

  • Serial Filter Implementation

  • Multi-Channel Filter Implementation

Day 2 - DSP for FPGAs

  • Frequency Domain Processing

  • Multirate Signal Processing for FPGAs

  • CORDIC Techniques

  • Numerically Controlled Oscillators

  • Numerically Controlled Oscillators

Day 3 - Generating HDL Code 

  • Preparing Models for HDL Code Generation

  • Fixed-Point Precision Control

  • Generating HDL Code for Multirate Models

  • Optimizing Generated HDL Code

Day 4 - Generating HDL Code

  • Using Native Floating Point 

  • Interfacing External HDL Code with Generated HDL

  • Verifying HDL Code with Cosimulation 

  • Hands-on demo