IEEE CASS-EDS-SSCS & SOEI-HUST Joint Technical Seminar No.48 “Research Progress on Clock and Interconnect Integrated Circuits for AI Scale-Up”

#PLL #CDR #OEIC #AI

In recent years, with the rise of artificial intelligence (AI), the demand of AI computing power has been growing rapidly. Significantly scaling-up AI computing power requires building high-performance distributed computing systems, which in turn demands high-speed interconnect chips to overcome communication bandwidth bottlenecks between AI processors. Currently, single-channel interconnect speeds have reached 112 Gb/s and are advancing toward 200 Gb/s and even 400 Gb/s, placing greater demands on a critical subsystem—clock integrated circuits. Clock integrated circuits include phase-locked loop (PLL) and clock and data recovery (CDR) circuits. For PLL, lower output clock jitter and low power consumption are essential. For CDR, high energy efficiency and minimal recovered clock jitter are required to ensure low bit error rates (e.g., below 10⁻¹²). Meanwhile, with the advancement of Chiplet technology, high-density and high-speed inter-chip interconnects have become increasingly important. Research into low-power, compact wired transceivers, including clock circuits, is critical for enabling high-density chip-to-chip interconnections. This talk first introduces the roles of various components in high-speed interconnect chips, followed by an overview of the team’s recent research progress over the past two years in PLL, CDR, chip-to-chip (C2C), and die-to-die (D2D) interconnect chips. Several of these results have been published in the top-tier conference ISSCC and the journal JSSC in the field of high-speed data transceiver ICs.

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• 1037 Luoyu Road
• HUST East Campus  
• Wuhan, Hubei
• China 430074
• Building: SOEI Building
• Room Number: D2-1 Meeting Room

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• Co-sponsored by Huazhong University of Science and Technology