Co-Packaged Optical Modules for HPC, Data Center and AI Applications
This event will be in-person only at McGill University. For the hybrid event, register via https://events.vtools.ieee.org/m/491772
Abstract :
This talk will cover the current status of co-packaging efforts, both VCSEL- and SiPh-based, where they fit into the Ethernet switch market and the evolving Computer IO market, and how these technologies are advancing HPC, Data Center, and AI applications. The emphasis will be on new requirements and challenges driven by AI systems.
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- McGill University
- 817 Sherbrooke St W
- Montreal, Quebec
- Canada H3A 0C3
- Building: Macdonald Engineering Building
- Room Number: MD267
- Click here for Map
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- Co-sponsored by McGill Optica Student Chapter
Speakers
Daniel M. Kuchta of Nvidia
Co-Packaged Optical Modules for HPC, Data Center and AI Applications
Abstract :
This talk will cover the current status of co-packaging efforts, both VCSEL- and SiPh-based, where they fit into the Ethernet switch market and the evolving Computer IO market, and how these technologies are advancing HPC, Data Center, and AI applications. The emphasis will be on new requirements and challenges driven by AI systems.
Biography:
Daniel M. Kuchta (IEEE Fellow 2019) is a Principal Hardware System Architect at Nvidia. Previously he was a Research Staff Member in the Communications and Computation Subsystems Department at the IBM Thomas J. Watson Research Center since 1992. He received B.S., M.S., and Ph.D. degrees in Electrical Engineering and Computer Science from the University of California at Berkeley in 1986, 1988, and 1992, respectively. While at IBM Research he has worked on high-speed VCSEL characterization, multimode fiber links, and parallel fiber optic link research. He received IEEE J. of Lightwave Technology best paper award in 2014 and in 2018 was the first recipient of the IEEE Photonics Technology Letters best paper award. He was Technical Program Chair for OFC 2018 and General Chair for OFC 2020. Dr. Kuchta is an author/coauthor of more than 145 technical papers and inventor/co-inventor of at least 40 patents
The presentation will be in English / La présentation sera en anglais.