Technical Talk on "High-Level Synthesis (HLS): A Technical Perspective on Next-Gen Hardware Design"

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The increasing complexity of modern digital systems demands design methodologies that can balance productivity, performance, and flexibility. Traditional RTL-based design flows, while powerful, are often time-consuming and error-prone when mapping algorithms into efficient hardware architectures. High-Level Synthesis (HLS) provides a transformative approach by enabling designers to describe hardware at a higher level of abstraction using languages such as C, C++, or SystemC.

This talk will introduce HLS concepts, design flow, and its role in bridging the gap between algorithm design and RTL implementation. We will explore the capabilities of HLS tools in hardware development, including support for custom datatypes, automatic scheduling, and integration with verification frameworks. Special focus will be given to optimization techniques at both the DataPath and control path levels, showcasing how careful architectural exploration can deliver high-performance and area-efficient designs. A key advantage of HLS is its left-shift verification capability, enabling functional validation and performance exploration early in the design flow, well before RTL is generated.

Through this session, attendees will gain insights into the advantages, challenges, and prospects of HLS, with examples drawn from domains such as signal processing, machine learning, and communication systems. The talk will conclude with an interactive Q&A session, encouraging participants to discuss how HLS can be leveraged effectively in their own projects.


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  • Dr. Pritam Bhattacharjee

    +918132863424


  Speakers

Dr. Indranil Hatai of Siemens EDA India Private Limited

Topic:

Technical Talk on "High-Level Synthesis (HLS): A Technical Perspective on Next-Gen Hardware Design"

Biography:

A person sitting in a chairDescription automatically generatedDr. Indranil Hatai is currently a Member of Consulting Staff in the Catapult C2GDS R&D Division at Siemens EDA India Private Limited, where he focuses on developing hardware-efficient architectures for DSP IP design.

Prior to this role, he served as a Senior Application Engineer at MathWorks India, where he worked extensively to accelerate adoption of MATLAB/Simulink-based HDL code generation and VLSI verification workflows across a range of domains including communications, signal processing, wireless systems, and machine/deep learning applications.

Dr. Hatai earned both his M.S. (by Research) and Ph.D. degrees in Microelectronics and VLSI Design from the Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology (IIT) Kharagpur, India. He subsequently completed a Post-Doctoral Fellowship at National University of Singapore (NUS), within the Green IC Design Centre, where he contributed to a 28nm TSMC chip tape-out for a Display Stream Compression Encoder.

He has been serving as the Course Instructor for the NPTEL MOOC course “Architectural Design of Digital Integrated Circuits” on the SWAYAM platform since 2018.

Dr. Hatai is also a recognized researcher, having received five Best Paper Awards and two National Awards for his contributions to the design and development of ASIC/FPGA-based systems.

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Agenda

  • Motivation: Why HLS?

  • Introduction to High-Level Synthesis (HLS)

  • Capabilities of HLS for Hardware Development

  • Optimization Opportunities

  • Case Studies & Applications

  • Q&A / Open Discussion